w83627sf Winbond Electronics Corp America, w83627sf Datasheet - Page 112

• Manufacturer Part Number: w83627sf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

CR23 (Default 0x00)
CR24 (Default 0b1s000s0s)
CR25 (Default 0x00)
enable bit (specified in CR24) is set.
This register contains enable bit for tri-state device's output pins when corresponding power down
Bit 7 - 1 : Reserved.
Bit 0
Bit 7
Bit 6
Bit 5 - 3 : Reserved.
Bit 2
Bit 1
Bit 0
Bit 7 - 6 : Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
: IPD (Immediate Power Down). When set to 1, it will put the whole chip into power down
mode immediately.
: Reserved.
: CLKSEL
= 0 The clock input on Pin 1 should be 24 Mhz.
= 1 The clock input on Pin 1 should be 48 Mhz.
The corresponding power-on setting pin is SOUTB (pin 83).
: ENKBC
= 0 KBC is disabled after hardware reset.
= 1 KBC is enabled after hardware reset.
This bit is read only, and set/reset by power-on setting pin. The corresponding power-on
setting pin is SOUTA (pin 54).
: Reserved
: PNPCSV
= 0 The Compatible PnP address select registers have default values.
= 1 The Compatible PnP address select registers have no default value.
When trying to make a change to this bit, new value of PNPCVS must be complementary
to the old one to make an effective change. For example, the user must set PNPCSV to 0
first and then reset it to 1 to reset these PnP registers if the present value of PNPCSV is 1.
The corresponding power-on setting pin is NDTRA (pin 52).
: URBTRI. For UART B device.
: URATRI. For UART A device.
: PRTTRI. For printer port device.
: Reserved.
: SCTRI. For Smart Card interface.
: FDCTRI. For FDC device.
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Publication Release Date: Nov. 2000
PRELIMINARY
W83627SF
Revision 0.60