w83627sf Winbond Electronics Corp America, w83627sf Datasheet - Page 104

• Manufacturer Part Number: w83627sf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

11.6 Smart Card Control Register (SCCR, write only at "base address + 3")
The Smart Card Control Register controls and defines the parity bit protocol for asynchronous data
communications.
Bit 7: BDLAB. When this bit is set to a logical 1 , designers can access the divisor (in 16-bit binary
Bit 6 - 5: Reserved. Always 0 when read.
Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3
Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will
Bit 2 – 0: Reserved. Bit 2 is always 0 and bit 1 – 0 are always 1 when read.
11.7 Interrupt Enable Register (IER, at "base address + 4")
This register contains global interrupt enable bit of Smart Card interface.
Bit 7 - 4: Reserved. Always 0 when read.
Bit 3: The Smart Card interface interrupt output is enabled by setting this bit to a logic 1.
Bit 2 – 0: Reserved. Always 0 when read.
format) from the divisor latches of the baudrate generator during a read or write operation. When
this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt
Control Register can be accessed.
is programmed. When this bit is set, an even number of logic 1's are sent or checked. When the
bit is reset, an odd number of logic 1's are sent or checked.
be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same position
as the transmitter will be detected.
7
7
0
6
0
6
0
0
0
5
5
0
4
4
3
3
2
0
2
0
1
0
1
1
0
1
0
0
Parity Bit Enable (PBE)
Even Parity Enable (EPE)
Baud rate Divisor Latch Access Bit (BDLAB)
IRQ enable
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Publication Release Date: Nov. 2000
PRELIMINARY
W83627SF
Revision 0.60