w83627sf Winbond Electronics Corp America, w83627sf Datasheet - Page 53

• Manufacturer Part Number: w83627sf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

DSKCHG (Bit 7):
This bit indicates the status of DSKCHG# input.
Bit 6-4: These bits are always a logic 1 during a read.
DMAEN (Bit 3):
This bit indicates the value of DO REGISTER bit 3.
NOPREC (Bit 2):
This bit indicates the value of CC REGISTER NOPREC bit.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
3.2.9
This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as
follows:
Bit 7-2: Reserved. These bits should be set to 0.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
In the PS/2 Model 30 mode, the bit definitions are as follows:
Bit 7-3: Reserved. These bits should be set to 0.
NOPREC (Bit 2):
This bit indicates no precompensation. It has no function and can be set by software.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
Configuration Control Register (CC Register) (Write base address + 7)
x
7
X: Reserved
X
7
X
x
6
:
Reserved
X
6
x
5
5
X
x
X
4
4
X
3
x
3
- 46 -
2
x
2
1
1
0
0
DRATE0
DRATE1
NOPREC
Publication Release Date: Nov. 2000
DRATE0
DRATE1
PRELIMINARY
W83627SF
Revision 0.60