w83627sf Winbond Electronics Corp America, w83627sf Datasheet - Page 105

• Manufacturer Part Number: w83627sf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

11.8 Smart Card Status Register (SCSR, at "base address + 5")
This 8-bit register provides information about the status of the data transfer during communication.
Bit 7: RFEI. This bit is set to a logic 1 when there is at least one parity bit error, no stop bit error or
Bit 6: TSRE. If the transmitting FIFO and TSR are both empty, it will be set to a logical 1. Otherwise,
Bit 5: TBRE. When a data character is transferred from TBR to TSR, this bit will be set to a logical 1. If
Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full
Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. When CPU
Bit 2: PBER. This bit is set to a logical 1 to indicate that parity bit of received data is incorrect. When
Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next
Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by CPU in the
silent byte detected in the FIFO. It is cleared by reading SCSR until there are no remaining errors
left in the FIFO.
this bit will be reset to a logical 0.
ETBREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write the next
data. It will be reset to a logical 0 when CPU writes data into TBR or FIFO.
word time, including start bit, data bits, parity bit, and stop bits. When the CPU reads SCSR, it
will clear this bit to a logical 0.
reads SCSR, it will clear this bit to a logical 0.
CPU reads SCSR, it will clear this bit to a logical 0.
received data before they were read by CPU. When CPU reads USR, it will clear this bit to a
logical 0.
RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
7
6
5
4
3
2
1
0
RBR Data Ready (RDR)
Overrun Error (OER)
Parity Bit Error (PBER)
No Stop bit Error (NSER)
Silent Byte Detected (SBD)
Transmitter Buffer Register Empty (TBRE)
Transmitter Shift Register Empty (TSRE )
RX FIFO Error Indication (RFEI)
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Publication Release Date: Nov. 2000
PRELIMINARY
W83627SF
Revision 0.60