lan91c100 Standard Microsystems Corp., lan91c100 Datasheet - Page 5

• Manufacturer Part Number: lan91c100
• Description: Feast ? Ast Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

PQFP/TQFP
PIN NO.
187-189
184
181
105
175
106
109
176
DESCRIPTION OF PIN FUNCTIONSOF PIN FUNCTIONSPIN FUNCTIONS
Write/nRea
d
nVL Bus
Access
Local Bus
Clock
Asynchron-
ous Ready
nSynchron-
ous Ready
nReady
Return
Interrupt
NAME
W/nR
nVLBUS
LCLK
ARDY
nSRDY
nRDYRTN
INT0-INT3
SYMBOL
BUFFER
OD16
TYPE
O16
O24
IP
I
I
I
5
Input. Defines the direction of synchronous
cycles. Write cycles when high, read cycles
when low.
Input.
synchronous bus interface is configured for
VL
LAN91C100 is configured for EISA DMA
burst
asynchronous bus interface.
Input. Used to interface synchronous buses.
Maximum frequency is 50 MHz. Limited to
8.33 MHz for EISA DMA burst mode.
Open drain output.
when interfacing asynchronous buses to
extend
completion) edge is controlled by the XTAL1
clock and therefore asynchronous to the
host CPU or bus clock.
Output.
interfacing
nVLBUS=0 to extend accesses. This signal
remains normally inactive, and its falling
edge indicates completion. This signal is
synchronous to the bus clock LCLK.
Input.
synchronous read cycles. In EISA burst
mode it is sampled on falling LCLK edges,
and synchronous cycles are delayed until it
is sampled high.
Outputs.
selected to be used; the other three are tri-
stated. The selection is determined by the
value
Configuration Register.
Bus
accesses.
of
This input is used to complete
When
accesses.
Only one of these interrupts is
This
INT
accesses.
synchronous
DESCRIPTION
low
output
SEL1-0
Does
ARDY may be used
Its
the
Otherwise
not
is
rising
bits
buses
used
LAN91C100
affect
in
(access
when
and
the
the
the