lan91c100 Standard Microsystems Corp., lan91c100 Datasheet - Page 34

• Manufacturer Part Number: lan91c100
• Description: Feast ? Ast Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

I/O SPACE - BANK1
RCV_BAD
received. When clear bad CRC packets do not
generate
released.
AUTO RELEASE When set, transmit pages are
released
transmission was successful (when TX_SUC is
set).
associated
successful packet numbers are not even written
into the TX COMPLETION FIFO. A sequence of
transmit packets will only generate an interrupt
when the sequence is completely transmitted
(TX EMPTY INT will be set), or when a packet in
the sequence experiences a fatal error (TX INT
will be set).
cleared and the transmission sequence stops.
The packet number that failed is the present in
the FIFO PORTS register, and its pages are not
released, allowing the CPU to restart the
sequence after corrective action is taken.
LE ENABLE Link Error Enable. When set it
enables the LINK_OK bit transition as one of the
interrupts merged into the EPH INT bit. Defaults
low (disabled). Writing this bit also serves as the
acknowledge by clearing previous LINK interrupt
conditions.
BYTE
BYTE
HIGH
LOW
OFFSET
In that case there is no status word
C
interrupts
by
ENABLE
When set, bad CRC packets are
with
LE
Upon a fatal error TXENA is
0
0
0
transmit
its
and
RCV_BAD
ENABLE
packet
CR
completion
0
0
their
CONTROL REGISTER
number,
ENABLE
memory
NAME
TE
0
0
0
if
and
the
is
34
X
X
CR ENABLE Counter Roll over Enable. When
set it enables the CTR_ROL bit as one of the
interrupts merged into the EPH INT bit. Defaults
low (disabled).
TE ENABLE Transmit Error Enable. When set
it enables Transmit Error as one of the
interrupts merged into the EPH INT bit. Defaults
low (disabled). Transmit Error is any condition
that clears TXENA with TX_SUC staying low as
described in the EPHSR register.
EEPROM SELECT This bit allows the CPU to
specify which registers the EEPROM RELOAD
or STORE refers to. When high, the General
Purpose Register is the only register read or
written.
Configuration, Base and Individual Address, and
STORE writes the Configuration and Base
registers.
RELOAD When set, it will read the EEPROM
and update relevant registers with its contents.
Clears upon completing the operation.
STORE When set, stores the contents of all
relevant registers in the serial EEPROM. Clears
upon completing the operation.
RELEASE
AUTO
X
0
READ/WRITE
When
EEPROM
SELECT
TYPE
X
0
low,
RELOAD
RELOAD
X
0
SYMBOL
CTR
STORE
0
0
0
reads