lan91c100 Standard Microsystems Corp., lan91c100 Datasheet - Page 24

• Manufacturer Part Number: lan91c100
• Description: Feast ? Ast Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

I/O SPACE - BANK 0
This register stores the status of the last frame transmitted. This register value, upon individual
transmit packet completion, is stored as the first word in the memory area allocated to the packet.
Packet interrupt processing should use the copy in memory as the register itself will be updated by
subsequent packet transmissions. The register can be used for real time values (like TXENA and
LINK OK). If TXENA is cleared the register holds the last packet completion status.
TXUNRN Transmit Under Run. Set if under run
occurs, it also clears TXENA bit in TCR.
Cleared by setting TXENA high. This bit should
never be set under normal operation.
LINK_OK General purpose input port driven by
nLNK pin inverted.
Test.
generates an interrupt.
RX_OVRN
asserts this bit and clears the FIFO.
receiver stays enabled. After a valid preamble
has been detected on a subsequent frame,
RX_OVRN is de-asserted. The RX_OVRN INT
bit in the Interrupt Status Register will also be
set and stay set until cleared by the CPU. Note
that receive overruns could occur only if receive
memory allocations fail.
CTR_ROL Counter Roll Over. When set, one
or more 4-bit counters have reached maximum
count (15).
register.
BYTE
BYTE
HIGH
LOW
OFFSET
A transition on the value of this bit
2
TX UNRN
TX DEFR
Upon FIFO overrun, the receiver
Cleared by reading the ECR
0
0
Typically used for LINK
-nLNK Pin
LINK_OK
LTX BRD
0
EPH STATUS REGISTER
RX_OVRN
SQET
NAME
0
0
The
CTR_ROL
16COL
24
0
0
EXC_DEF
last/current transmit was deferred for more than
1518 * 2 byte times. Cleared at the end of every
packet sent.
LOST_CARR Lost Carrier Sense. When set,
indicates that Carrier Sense was not present at
end of preamble.
enabled. This condition causes TXENA bit in
TCR to be reset. Cleared by setting TXENA bit
in TCR.
LATCOL Late collision detected on last transmit
frame. If set, a late collision was detected (later
than 64 byte times into the frame).
detected, the transmitter JAMs and turns itself
off, clearing the TXENA bit in TCR. Cleared by
setting TXENA in TCR.
TX_DEFR
carrier was detected during the first 6.4 sec of
the inter frame gap. Cleared at the end of every
packet sent.
LTX_BRD Last transmit frame was a broadcast.
LTX MULT
EXC_DEF
0
0
READ ONLY
Transmit Deferred.
Excessive Deferral.
MUL COL
TYPE
CARR
LOST
0
0
Valid only if MON_CSN is
LATCOL
SNGL
COL
0
0
SYMBOL
EPHSR
When set,
When set
TX_SUC
X
0
When