lan91c100 Standard Microsystems Corp., lan91c100 Datasheet - Page 4

• Manufacturer Part Number: lan91c100
• Description: Feast ? Ast Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

PQFP/TQFP
173-170,
168-166,
142-139,
137-135,
131-129,
115-112,
164,144,
127,126,
124,123,
121,118,
PIN NO.
148-159
145-147
160-163
133,
117,
193
110
182
183
95
DESCRIPTION OF PIN FUNCTIONSOF PIN FUNCTIONSPIN FUNCTIONS
Address
Address
Address
Enable
nByte
Enable
Data Bus
Reset
nAddress
Strobe
nCycle
NAME
A4-A15
A1-A3
AEN
nBE0-nBE3
D0-D31
RESET
nADS
nCYCLE
SYMBOL
BUFFER
TYPE
I/O24
IS
IS
I
I
I
I
I
4
Input. Decoded by the LAN91C100 to
determine accesses to its registers.
Input. Used by the LAN91C100 for internal
register selection.
Input. Used as an address qualifier. Address
decoding is only enabled when AEN is low.
Input. Used during LAN91C100 register
accesses to determine the width of the
access and the register(s) being accessed.
nBE0-nBE3 are ignored when nDATACS is
low
transfers are assumed.
Bidirectional. 32 bit data bus used to access
the LAN91C100's internal registers. Data
bus has weak internal pullups. Supports
direct connection to the system bus without
external buffering. For 16 bit systems, only
D0-D15 are used.
Input. This input is not considered active
unless it is active for at least 100ns to filter
narrow glitches.
Input. Address strobe. For systems that
require address latching, the rising edge of
nADS indicates the latching moment for A1-
A15 and AEN. All LAN91C100 internal
functions of A1-A15, AEN are latched except
for nLDEV decoding.
Input. This active low signal is used to
control
cycles.
(burst
LAN91C100
accesses)
DESCRIPTION
synchronous
because
32
bus
bit