lan91c100 Standard Microsystems Corp., lan91c100 Datasheet - Page 27

• Manufacturer Part Number: lan91c100
• Description: Feast ? Ast Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

I/O SPACE - BANK 0
Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All
counters are cleared when reading the register, and do not wrap around beyond 15.
Each 4-bit counter is incremented every time the
corresponding event, as defined in the EPH
STATUS REGISTER bit description, occurs.
Note that the counters can only increment once
per enqueued transmit packet, never faster;
limiting the rate of interrupts that can be
generated by the counters. For example, if a
packet is successfully transmitted after one
collision, the SINGLE COLLISION COUNT field
is incremented by one. If a packet experiences
between two to 16 collisions, the MULTIPLE
COLLISION COUNT field is incremented by
one.
BYTE
BYTE
HIGH
LOW
OFFSET
6
0
0
NUMBER OF EXC. DEFERRED TX
MULTIPLE COLLISION COUNT
0
0
COUNTER REGISTER
NAME
0
0
27
0
0
If a packet experiences deferral, the NUMBER
OF DEFERRED TX field is incremented by one,
even if the packet experienced multiple deferrals
during its collision retries.
The
maintaining statistics in the AUTO RELEASE
mode
generated on successful transmissions.
Reading the register in the transmit service
routine will be enough to maintain statistics.
0
0
COUNTER
where
NUMBER OF DEFERRED TX
SINGLE COLLISION COUNT
READ ONLY
TYPE
no
0
0
transmit
REGISTER
0
0
interrupts
SYMBOL
ECR
facilitates
0
0
are