mc33905s Freescale Semiconductor, Inc, mc33905s Datasheet - Page 67

• Manufacturer Part Number: mc33905s
• Description: System Basis Chip Gen2 With High Speed Can And Lin Interface
• Manufacturer: Freescale Semiconductor, Inc

WATCHDOG AND MODE REGISTERS
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 24. Watchdog refresh register, W/D
Table 25. MODE Register, MODE
Notes
24.
.
[b_15 b_14] 01_101 [P/N]
[b_15 b_14] 01_110 [P/N]
MOSI First Byte [15-8]
MOSI First Byte [15-8]
Condition for default
The Simple Watchdog Refresh command is in hexadecimal: 5A00. This command is used to refresh the W/D and also to transition
from INIT mode to Normal Mode, and from Normal Request Mode to Normal mode (after a wake up of a reset)
01 01_ 101 P
01 01_ 110 P
Default state
Default state
Table 26.
b7, b6, b5, b4, b3
b2, b1, b0
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000
1 1001
1 1010
1 1011
1 1100
1 1101
1 1110
1 1111
Low Power Vdd OFF selection and FWU / Cyclic Sense selection
Mode[4]
b7, b6, b5, b4, b3
bit 7
bit 7
N/A
0
0
0 1100
0 1101
0 1110
0 1111
Low Power Vdd ON selection and operation mode
Mode[3]
bit 6
bit 6
N/A
0
0
Random Code inverted, these 3bits are the inverted bits obtained from the
previous SPI command.
Mode[2]
FWU
ON
ON
ON
ON
ON
ON
ON
ON
off
off
off
off
off
off
off
off
bit 5
bit 5
N/A
0
0
MOSI Second Byte, bits 7-0
MOSI Second Byte, bits 7-0
Mode[1]
Cyclic Sense
bit 4
bit 4
N/A
0
0
ON
ON
ON
ON
ON
ON
ON
ON
off
off
off
off
off
off
off
off
FWU
ON
ON
off
off
POR
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Mode[0]
bit 3
bit 3
N/A
0
0
Cyclic INT
ON
ON
ON
ON
ON
ON
ON
ON
off
off
off
off
off
off
off
off
Rnd_b[2]
bit 2
bit 2
N/A
0
0
SERIAL PERIPHERAL INTERFACE
Cyclic Sense
ON
ON
off
off
Watchdog
Rnd_b[1]
bit 1
bit 1
ON
ON
ON
ON
ON
ON
ON
ON
N/A
off
off
off
off
off
off
off
off
0
0
Rnd_b[0]
bit 0
bit 0
N/A
0
0
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