mc33905s Freescale Semiconductor, Inc, mc33905s Datasheet - Page 48

• Manufacturer Part Number: mc33905s
• Description: System Basis Chip Gen2 With High Speed Can And Lin Interface
• Manufacturer: Freescale Semiconductor, Inc

Pattern Wake-up
receiver must receive a series of 3 consecutive valid
dominant pulses, by default when the CANWU bit is low.
CANWU bit can be set high by SPI and the wake-up will occur
after a single pulse duration of 2μs (typ).
.
BUS TERMINATION
terminations:
• Differential termination resistors between CANH and
48
33904/5
CAN INTERFACE
CAN INTERFACE DESCRIPTION
The device supports the two main types of bus
CANL lines.
In order to wake-up the CAN interface, the wake-up
CAN
bus
CAN
bus
Dominant Pulse # n: duration 1 or multiple dominant bits
Tcan wu3-f
Dominant
Pulse # 1
Figure 30. Pattern Wake-up - Multiple Dominant Detection
Internal wake-up signal
Internal differential wake-up receiver signal
Figure 29. Single Dominant Pulse Wake-up
Tcan wu1-f
Internal differential wake-up receiver signal
CANH
CANL
Internal wake-up signal
Dominant
Pulse # 1
Tcan wu3-to
Tcan wu3-f
Dominant
Pulse # 2
CANH
CANL
Can wake up detected
3 pulses should occur in a time frame of 120μs, to be
considered valid. When 3 pulses meet these conditions, the
wake signal is detected. This is illustrated by the following
figure.
• SPLIT termination concept, with the mid point of the differ-
• In application, device can also be used without termina-
A valid dominant pulse should be longer than 500ns. The
ential termination connected to GND through a capacitor
and to the SPLIT pin.
tion.
Tcan wu3-f
Dominant
Pulse # 3
Dominant
Pulse # 2
Can wake up detected
Analog Integrated Circuit Device Data
Dominant
Pulse # 4
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