mc33905s Freescale Semiconductor, Inc, mc33905s Datasheet - Page 66

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mc33905s

Manufacturer Part Number
mc33905s
Description
System Basis Chip Gen2 With High Speed Can And Lin Interface
Manufacturer
Freescale Semiconductor, Inc
Datasheet
66
33904/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 22. Timer Register C, Watchdog LP Mode or Flash Mode and Forced Wake-up Timer, TIM_C
[b_15 b_14] 01_100 [P/N]
Table 23. Typical Timing Values
MOSI First Byte [15-8]
Condition for default
01 01_ 100 P
Default state
b7
b7
b3
0
1
0
1
0
1
48 (def)
48 (def)
000
000
256
000
12
16
64
WD-LP-F[3]
bit 7
0
001
001
512
001
128
24
32
96
96
Watchdog in Low Power V
WD-LP-F[2]
bit 6
0
Watchdog in Flash Mode
1024
010
010
192
010
192
258
48
64
Forced Wake Up
WD-LP-F[1]
bit 5
0
2048
011
128
011
384
011
384
512
96
WD-LP-F[0]
MOSI Second Byte, bits 7-0
b6, b5, b4
b6, b5, b4
b2, b1, b0
bit 4
DD
0
(in ms)
ON Mode
(in ms)
4096
1024
100
192
256
100
768
100
768
POR
FWU[3]
bit 3
0
(in ms)
1536
8192
1536
2048
101
384
512
101
101
Analog Integrated Circuit Device Data
FWU[2]
bit 2
0
16384
1024
3072
3072
4096
110
768
110
110
Freescale Semiconductor
FWU[1]
bit 1
0
32768
1536
2048
6144
6144
8192
111
111
111
FWU[0]
bit 0
0

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