mc33905s Freescale Semiconductor, Inc, mc33905s Datasheet - Page 63

• Manufacturer Part Number: mc33905s
• Description: System Basis Chip Gen2 With High Speed Can And Lin Interface
• Manufacturer: Freescale Semiconductor, Inc

Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 18. Initialization Miscellaneous Functions, INIT MISC (note: register can be written only in INIT mode)
Notes
23.
b2, b1, b0
[b_15 b_14] 0_1000 [P/N]
MOSI First Byte [15-8]
100
101
110
111
Bit
0xx
Condition for default
b7
b6
b5
b4
b3
0
1
0
1
0
1
0
1
Bits b2,1 and 0 allow the following operation:
First, check the resistor device has detected at the Debug pin. If the resistor is different, bit 5 (Debug resistor) is set in INTerrupt
register (ref to device flag table).
Second, over write the resistor decoded by device, to set the SAFE mode operation by SPI. Once this function is selected by bit 2 =1,
this selection has higher priority than “hardware”, and device will behave according to b2,b1 and b0 setting
01 01_ 000 P
Default state
Dbg Res[2], Dbg Res[1], Dbg Res[0] - Allow verification of the external resistor connected at DBG terminal. Ref to parametric table for resistor
LPM w RND - Select the functionality to change mode (enter in Low Power) using the device Random Code
LPM w RND
100 verification enable: resistor at DBG terminal is typ 68kohms (RB3) - Selection of SAFE mode B3
110 verification enable: resistor at DBG terminal is typ 15kohms (RB1) - Selection of SAFE mode B1
Function enable: an INT pulse will occur at 50% of the Watchdog Period when device in flash mode.
101 verification enable: resistor at DBG terminal is typ 33kohms (RB2 - Selection of SAFE mode B2
bit 7
111 verification enable: resistor at DBG terminal is typ 0kohms (RA) - Selection of SAFE mode A
0
Function disable: the Low Power mode can be entered without usage of Random Code
INT flash - Select INT pulse generation at 50% of the Watchdog Period in Flash mode
Function disable: the parity is not used. The parity bit must always set to logic 0.
INT pulse duration is typ 100μs. Ref to dynamic parameter table for exact value.
INT pulse duration is typ 25μs. Ref to dynamic parameter table for exact value.
Function enabled: the Low Power mode is entered using the Random Code
SPI parity
INT terminal will assert a low level pulse, duration selected by bit [b4]
INT pulse -Select INT terminal operation: low level pulse or low level
bit 6
Function enable: the parity is used, and parity must be calculated.
0
SPI parity - Select usage of the parity bit in SPI write operation
INT terminal assert a permanent low level (no pulse)
INT pulse
INT width - Select the INT pulse duration
bit 5
0
Function disable
Function disable
Description
INT width
range value.
MOSI Second Byte, bits 7-0
bit 4
POR
DETAIL OF CONTROL BITS AND REGISTER MAPPING
INT flash
bit 3
0
Dbg Res[2]
bit 2
0
SERIAL PERIPHERAL INTERFACE
Dbg Res[1]
bit 1
0
Dbg Res[0]
bit 0
0
33904/5
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