mpc82g516a Megawin Technology, mpc82g516a Datasheet - Page 87

• Manufacturer Part Number: mpc82g516a
• Description: 8-bit Microcontroller
• Manufacturer: Megawin Technology

18.2 WDT Operation
The WDT is by default disabled after power-on reset. To enable the WDT, the user must set the ENW bit. When
the WDT is enabled, the user needs to service it by setting the CLW bit to clear the WDT counter and avoid an
overflow. The 15-bit WDT counter will overflow when it reaches 32767 (7FFFH) and this will reset the device. And,
when the WDT is enabled, it will increment every 12 system clock cycles (12/Fosc) while the oscillator is running.
This means the user must clear the WDT counter at least every 32767 x12 system cock cycles.
The WDT in this device is one-time enabled. The so-called “one-time enabled” means:
by setting ENW bit, there is no way to disable it except through power-on reset, which will clear the ENW bit.
the WDTCR register will keep the previous programmed value unchanged after any resets (including hardware
reset, software reset and WDT reset) except the power-on reset. For example, if the WDTCR is 0x2D, it still
keeps at 0x2D rather than 0x00 after resets. Only power-on reset can initialize it to 0x00. In other words, the
WDT can only be disabled by a power-on reset. Thus it is called “one-time enabled” WDT.
The WDT overflow period is determined by the formula:
Table 18-1 shows the WDT overflow period for MCU running at 6/12/24MHz. The period is the maximum interval
for the user to clear the WDT to prevent from chip reset.
Table 18-1. WDT Overflow Period
18.3 Sample Code for WDT
Condition: WDT Overflow Period = 1.048 seconds @Fosc=12MHz
87
WDTCR_buf
start:
main_loop:
PS2 PS1 PS0
0
0
0
0
1
1
1
1
2
15
0
0
1
1
0
0
1
1
x Prescaler x (12 / Fosc)
;...
MOV
ORL
ANL
MOV
ORL
MOV
ORL
MOV
;...
;...
JMP
DATA
0
1
0
1
0
1
0
1
30h
WDTCR_buf,#00h
WDTCR_buf,#04h
WDTCR_buf,#0FCh ;PS1=0,PS0=0
WDTCR,WDTCR_buf
WDTCR_buf,#20h
WDTCR,WDTCR_buf
WDTCR_buf,#10h
WDTCR,WDTCR_buf
main_loop
Prescaler value
128
256
16
32
64
2
4
8
;declare a buffer for WDTCR register
;(because WDTCR is a Write-only register)
;initialize the WDTCR buffer
;PS2=1
;write to WDTCR
;ENW=1
;write to WDTCR register
;CLRW=0
;write to WDTCR register
MPC82G516A Data Sheet
Fosc=6MHz
131.072 ms
262.144 ms
524.288 ms
16.778 s
1.048 s
2.097 s
4.194 s
8.389 s
(PS2,PS1,PS0)=(1,0,0), prescaler=32
Fosc=12MHz
131.072 ms
262.144 ms
524.288 ms
65.536 ms
enable WDT
clear WDT counter
1.048 s
2.097 s
4.194 s
8.389 s
Once the WDT is enabled
Fosc=24MHz
131.072 ms
262.144 ms
524.288 ms
32.768 ms
65.536 ms
1.048 s
2.097 s
4.194 s
MEGAWIN
And,