mg84fl54b Megawin Technology, mg84fl54b Datasheet
mg84fl54b
Related parts for mg84fl54b
mg84fl54b Summary of contents
Page 1
... Additional External Interrupts (INT2 and INT3)............................................................... 39 This document contains information on a new product under development by Megawin. Megawin reserves the right to change or discontinue this product without notice. © Megawin Technology Co., Ltd. 2005 All right reserved. Preliminary MG84FL54B Full-Speed USB micro-controller 2008/Apr. version 0.98 MEGAWIN ...
Page 2
... USB SFR Description ...............................................................................................69 20. In-System-Programming (ISP)........................................................................................76 20.1. Description for ISP Operation ................................................................................77 20.2. Demo Program for ISP ..........................................................................................78 21. In-Application-Programming (IAP) ..................................................................................79 21.1. IAP-memory Boundary/Range ............................................................................... 79 21.2. Update the data in the IAP-memory....................................................................... 79 22. System Clock..................................................................................................................80 22.1. Programmable System Clock ................................................................................ 80 22.2. On-chip XTAL Oscillating Driving Control .............................................................. 81 23. Power-On Reset .............................................................................................................82 2 MG84FL54B Data Sheet MEGAWIN ...
Page 3
... Logic Operations.................................................................................................... 87 25.3. Data Transfer.........................................................................................................88 25.4. Boolean Variable Manipulation .............................................................................. 89 25.5. Program and Machine Control ...............................................................................90 26. Absolute Maximum Rating..............................................................................................91 27. Electrical Characteristics ................................................................................................91 27.1. Global DC Electrical Characteristics ...................................................................... 91 27.2. USB Transceiver Electrical Characteristics ........................................................... 92 28. Field Applications............................................................................................................93 29. Order Information............................................................................................................93 30. Package Dimension........................................................................................................93 31. Revision History.............................................................................................................. 94 MEGAWIN MG84FL54B Data sheet 3 ...
Page 4
... General Description MG84FL54B is an enhanced single-chip 8-bit microcontroller manufactured in an advanced Embedded-Flash process. The instruction set is fully compatible with that of the 8051. With the enhanced CPU core, the device needs only clock cycles to complete an instruction, and thus provides much higher performance than the standard 8051, which needs clock cycles to complete an instruction ...
Page 5
... Maximum operating frequency - Up to 24MHz, Industrial range Flash Quality criterion: - Flash data endurance: 20K erase/write cycles - Flash data retention: 100 years under room temperature 2-level code protection: SB (code scrambled) & LOCK (code locked) Package: LQFP-48 *: Tested by sampling. MEGAWIN MG84FL54B Data sheet 5 ...
Page 6
... Port3 Driver P4.0 ~ P4.3 P3.0 ~ P3.7 6 XRAM576 1-T 8051 RAM256 CPU Core Port2 Latch Port1 Latch Port2 Driver Port1 Driver P2.0 ~ P2.7 P1.0 ~ P1.7 MG84FL54B Block Diagram MG84FL54B Data Sheet Two Wire Dual DPTR Serial Interface ISP/IAP SPI 16KB Flash Key Pad Timer2 Input Logic eUART Port0 Latch Timer0/1 Interrupt ...
Page 7
... VDDA VSSA 4 P43 5 P42 6 P41 7 VDD_PLL 8 PLL_CV 9 RXD/P30 10 TXD/P31 11 INT0/P32 MEGAWIN MG84FL54BD 31 LQFP48 MG84FL54B Data sheet RST P05/KBI5 P04/KBI4 P03/KBI3 P02/KBI2 P01/KBI1 P00/KBI0 P17 P16 P15 P14 P13 7 ...
Page 8
... P3.5 & Timer 1 external input. P3.6 & External interrupt 2. P3.7 & External interrupt 3. P2.2. P2.3. P Digital power for I/O pads. P Digital power for I/O internal core logic. P1.0 & Timer 2 clock output. P1.1 P1.2. P1.3. P1.4. P1.5. P1.6. P1.7. P0.0 & Keypad input 0. P0.1 & Keypad input 1. P0.2 & Keypad input 2. P0.3 & Keypad input 3. MG84FL54B Data Sheet MEGAWIN ...
Page 9
... P0.4 & Keypad input 4. P0.5 & Keypad input 5. I System reset input, high active. P0.6 & Keypad input 6. P0.7 & Keypad input 7. P2.0 & TWSI_SCL. P2.1 & TWSI_SDA. P4.0 Digital ground. Crystal output pad. I Crystal input pad. P2.4 & SPI_ SSI. P2.5 & SPI_MOSI. P2.6 & SPI_MISO. P2.7 & SPI_CLK. MG84FL54B Data sheet 9 ...
Page 10
... IFADRH IFADRL SIDAT SISTA RCAP2L RCAP2H TL2 P3M1 P4M0 P4M1 P1M1 P0M0 P0M1 TL0 TL1 TH0 DPL DPH SPSTAT 2/A 3/B 4/C MG84FL54B Data Sheet 5/D 6/E 7/F SCMD ISPCR KBPATN KBCON KBMASK TH2 CKCON CKCON2 AUXIE AUXIP AUXR2 TSTWD P2M0 P2M1 TH1 AUXR SPCTL SPDAT PCON ...
Page 11
... TF2 EXF2 RCLK 8CH 8AH 8DH 8BH CDH CCH CBH CAH 9FH 9EH 9DH 98H SM0/FE SM1 SM2 99H 87H SMOD SMOD0 - MG84FL54B Data sheet Bit-4 Bit-3 Bit-2 Bit-1 D4H D3H D2H D1H RS1 RS0 OV - 84H 83H 82H 81H P0.4 P0.3 P0.2 P0.1 KBI4 KBI3 ...
Page 12
... BRADJ0 A6H T0X12 T1X12 URM0x6 C9H T2CPCF - DUTY1 C7H XCKS4 XCKS3 XCKS2 BFH - - OSCDR0 E1H WRF - ENW E7H ISPEN SWBS SWRST MG84FL54B Data Sheet Bit-4 Bit-3 Bit-2 Bit-1 C4H C3H C2H C1H IT3 IL2 EX2 IE2 - - - - - - - - ECH EBH EAH E9H - P4.3 P4 ...
Page 13
... ISP Flash Address IFADRH High IFADRL ISP Flash Address Low IFD ISP Flash Data ISP Sequential SCMD Command Notes: *: bit addressable -: reserved bit MEGAWIN E3H E4H E2H E6H MG84FL54B Data sheet 00H 00H FFH xxH 13 ...
Page 14
... Flash Memory Configuration There are total 16K bytes of Flash Memory. Note: (default) 2KB ISP code present, 1KB IAP space configured, Lock enabled 14 . MG84FL54B Data Sheet MEGAWIN ...
Page 15
... After being compiled, the variables declared by “pdata” and “xdata” will become the memories accessed by “MOVX @Ri” and “MOVX @DPTR”, respectively. Thus the BA126 hardware can access them correctly. The user can get the following descriptions from the “Keil Software — Cx51 Compiler User’s Guide”. MEGAWIN MG84FL54B Data sheet 15 ...
Page 16
... DPS: DPTR select bit, used to switch between DPTR0 and DPTR1. The DPS bit status should be saved by software when switching between DPTR0 and DPTR1. DPS (82h) DPS=0 DPL DPL DPS=1 Selected by DPS (AUXR1, bit0 T2X12 DPTR selected DPTR0 DPTR1 MG84FL54B Data Sheet External Data Memory DPS MEGAWIN ...
Page 17
... P1M0.4 P1M0.3 P1M0 P1M1.4 P1M1.3 P1M1 P2M0.4 P2M0.3 P2M0 P2M1.4 P2M1.3 P2M1 P3M0.4 P3M0.3 P3M0 P3M1.4 P3M1.3 P3M1.2 MG84FL54B Data sheet P0M0.1 P0M0 P0M1.1 P0M1 P1M0.1 P1M0 P1M1.1 P1M1 P2M0.1 P2M0 P2M1 ...
Page 18
... VDD. The pull-down for this mode is the same as for the quasi- bidirectional mode. In addition, the input path of the port pin in this configuration is also the same as quasi- bidirectional mode P4M0.3 P4M0 P4M1.3 P4M1.2 MG84FL54B Data Sheet 1 0 P4M0.1 P4M0 P4M1.1 P4M1.0 MEGAWIN ...
Page 19
... Input-Only (Hi-Z) The input-only configuration is a Schmitt-triggered input without any pull-up resistors on the pin. MEGAWIN MG84FL54B Data sheet 19 ...
Page 20
... That means that the device can source total 40mA and sink total 40mA at the same time without causing any damage to itself. 20 MG84FL54B Data Sheet MEGAWIN ...
Page 21
... Set to select Fosc as the clock source, and clear to select Fosc/12. T0CKOE: Set to enable Timer 0 clock output on P3.4. The following figures show the selection of alternate clock source for Timer 0 and Timer1. 10.1.1. Mode 0: 13-bit Counter Where OSC means Fosc, the system clock. MEGAWIN MG84FL54B Data sheet T0CKOE 21 ...
Page 22
... Mode 1: 16-bit Counter Where OSC means Fosc, the system clock. 10.1.3. Mode 2: 8-bit Auto-reload Where OSC means Fosc, the system clock. 22 MG84FL54B Data Sheet MEGAWIN ...
Page 23
... T0CKOE to “1”. Of course, the bit TR0 (TCON.4) must also be set to start the timer. For a 12 MHz system clock, Timer 0 has a programmable output frequency range of 1953 MHz. The clock frequency is equal to (Timer 0 overflow rate / 2), that is Clock freq. = where, (Fosc is the system clock.) MEGAWIN Fosc n x (256-TH0) n=24 if T0X12=0 n=2 if T0X12=1 MG84FL54B Data sheet 23 ...
Page 24
... Timer 2 overflows or negative transitions at T2EX pin when EXEN2=1. When either RCLK=1 or TCLK=1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow T2X12 - TCLK EXEN2 TR2 MG84FL54B Data Sheet DPS 1 0 T2OE DCEN 1 0 C/T2 CP/-RL2 MEGAWIN ...
Page 25
... Baud-rate generator 0 0 16-bit capture 0 0 16-bit auto-reload (counting-up only) 16-bit auto-reload (counting-up or counting down Clock output TL2 TH2 (8 BITS) (8 BITS) TR2 RCAP2L RCAP2H EXEN2 Timier2 in Capture Mode MG84FL54B Data sheet Mode TF2 Timer2 Interrupt EXF2 25 ...
Page 26
... An overflow on Timer2 or 1-to-0 transition on T2EX pin will load RCAP2H and RCAP2L contents onto Timer2, also set TF2 and EXF2, respectively. Fosc/12 C/T2=0 C/T2=1 T2 pin Transition Detector T2 EX pin 26 TL2 TH2 (8 BITS) (8 BITS) TR2 RELOAD RCAP2L RCAP2H EXEN2 Timier2 in Auto Reload Mode (DCEN=0) MG84FL54B Data Sheet TF2 Timer2 Interrupt EXF2 MEGAWIN ...
Page 27
... RCAP2H and RCAP2L. But if counting direction is UP, an overflow of timer2 loads RCAP2H,RCAP2L contents onto Timer2. Fosc/12 C/T2=0 C/T2=1 T2 pin MEGAWIN FFH FFH TL2 TH2 TR2 RCAP2H RCAP2L Timier2 in Auto Reload Mode (DCEN=1) MG84FL54B Data sheet EXF2 TF2 interrupt Count Direction DOWN T2EX PIN Timer2 27 ...
Page 28
... Transition Detector T2 EX pin EXEN2 28 TL2 TH2 (8 BITS) (8 BITS) TR2 RCAP2L RCAP2H Timer2 Interrupt EXF2 Timier2 in Baud Rate Generator Mode MG84FL54B Data Sheet Timer 1 overflow 2 “0” “1” SMOD “1” “0” RCLK RX Clock “1” “0” TCLK ...
Page 29
... It is possible to use Timer baud rate generator and a clock generator simultaneously. Note, however, in this configuration, the baud rates and clock frequencies are not independent since both functions use the same reload values in the [RCAP2H, RCAP2L] registers. MEGAWIN = - out Frequency 4 x (65536 MG84FL54B Data sheet Fosc - [RCPA2H, RCAP2L]) 29 ...
Page 30
... Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the REN TB8 RB8 POF GF1 GF0 MG84FL54B Data Sheet IDL MEGAWIN ...
Page 31
... Broadcast address of all “don’t cares”. This effectively disables the Automatic Addressing mode and allows the micro-controller to use standard 80C51 type UART drivers which do not make use of this feature. MEGAWIN MG84FL54B Data sheet 31 ...
Page 32
... Bits T1X12 and URM0X6 provide a new option for the baud rate setting, as listed below. Baud Rate in Mode 0 URM0X6 = 0 Fosc B. (The same as standard 8051 POF GF1 GF0 T2X12 Enhanced Baud Rate Setting Default Baud Rate Double Baud Rate MG84FL54B Data Sheet IDL DPS T0CKOE URM0X6 = 1 Fosc B. MEGAWIN ...
Page 33
... Baud Rate = (2/16) x 12MHz / (256-243) = 115385 bps. Where, the deviation to the standard 115200 bps is +0.16%, which is acceptable in an UART communication. MEGAWIN x Fosc BRADJ = 0 Fosc (256-TH1) 32 SMOD Fosc 256-TH1 MG84FL54B Data sheet BRADJ = 1 SMOD 2 x Fosc B. BRADJ = 1 SMOD Fosc (256-TH1) ...
Page 34
... Note2: For Fosc=12MHz, if BRADJ=1 and [RCAP2H,L]=65523, then we can get: Baud Rate = (12MHz/8) x 1/(65536-65523) = 115385 bps. Where, the deviation to the standard 115200 bps is +0.16%, which is acceptable in UART communication B.R. = MG84FL54B Data Sheet BRADJ = 1 Fosc 65536-[RCAP2H,RCAP2L] Note2 ...
Page 35
... EX2 IE2 PX2 EX3 IE3 PX3 ESPI SPIF PSPI - - - - - - - - EKBI KBIF PKBI ETWSI SI PTWSI EUSB (See Note1) PUSB ET1 EX1 MG84FL54B Data sheet Polling Vector Priority Address (Highest) 0003H . 000BH 0013H . . 001BH PS . 0023H . 002BH . 0033H . 003BH . 0043H - . 004BH - . 0053H - . ...
Page 36
... AUXIP (Address=AEH, Auxiliary Interrupt Priority Register PUSB PTWSI PKBI PUSB: USB interrupt priority bit. PTWSI: 2-wire-Serial-Interface interrupt priority bit IT3 IL2 EX2 PT1 PX1 MG84FL54B Data Sheet ESPI 1 0 IE2 IT2 1 0 PT0 PX0 PSPI MEGAWIN ...
Page 37
... Level 1 (high priority) 0 Level 0 (low priority) Table: Priority Level Determined by [ AUXIP ] AUXIP.x Interrupt Priority Level 1 Level 1 (high priority) 0 Level 0 (low priority) For example, if (IP.3)=(1), then Timer 1 has the priority level equal to 1, which is higher than level 0 with (IP.3)=(0). MEGAWIN MG84FL54B Data sheet 37 ...
Page 38
... The low-level triggered external interrupts, /INT0, /INT1, INT2 and INT3, should keep active until the ISP/IAP is complete, or they will be neglected Register IP Register IE0 IE1 Global Enable MG84FL54B Data Sheet High Priority Level Interrupt Interrupt Polling Sequence Low Priority Level Interrupt MEGAWIN ...
Page 39
... PS: Serial Port interrupt priority bit. PT1: Timer 1 interrupt priority bit. PX1: External interrupt 1 priority bit. PT0: Timer 0 interrupt priority bit. PX0: External interrupt 0 priority bit. MEGAWIN IT3 IL2 EX2 PT1 PX1 MG84FL54B Data sheet 1 0 IE2 IT2 1 0 PT0 PX0 39 ...
Page 40
... KBMASK.2: When set, enables P0 cause of a Keypad Interrupt. KBMASK.1: When set, enables P0 cause of a Keypad Interrupt. KBMASK.0: When set, enables P0 cause of a Keypad Interrupt MG84FL54B Data Sheet PATN_SEL KBIF 1 0 MEGAWIN ...
Page 41
... Once the CPU is wakened up, the interrupt service routine is serviced until the “RETI” instruction is encountered, and, the next instruction to be executed will be the one following the instruction that put the CPU into power- down mode. MEGAWIN EA MG84FL54B Data sheet Wake up CPU 41 ...
Page 42
... MCU will wake up, enter "IE0_isr", ;and then return here to run continuously ! ;... ;... ; 42 ;P3.2 ;IE.7 ;IE.0 ;/INT0 interrupt vector, address=0003h ;pull high P3.2 ;clear /INT0 interrupt flag ;may select falling-edge/low-level triggered ;enable global interrupt ;enable /INT0 interrupt ;put MCU into power-down mode ;! Note: here must be a NOP MG84FL54B Data Sheet MEGAWIN ...
Page 43
... Receive Data Intput Shift Buffer Register SPI Control SSIG SPEN DORD MSTR CPOL CPHA SPIF THRE SYNCEN CKOD SPI block diagram 4 3 MSTR CPOL CPHA MG84FL54B Data sheet P2.6 (MISO) P2.5 (MOSI) I/O control P2.7 (SPICLK) P2.4 (SS) SPCTL SPR1 SPR0 SPSTAT SSPOL SPR2 SPR1 SPR0 ...
Page 44
... For reading from: SPDAT is the input shift register containing the received data. 44 100: Fosc/16 001: Fosc/6 101: Fosc/24 010: Fosc/8 110: Fosc/48 011: Fosc/12 111: Fosc/ MG84FL54B Data Sheet (Where, Fosc is the system clock SPR2 (LSB) MEGAWIN ...
Page 45
... Two devices are connected to each other and either device can be a master or a slave. When no SPI operation is occurring, both can be configured as masters with MSTR=1, SSIG=0 and P2.4 (/SS) configured in quasi- bidirectional mode. When any device initiates a transfer, it can configure P2 output and drive it low to force a “mode change to slave” in the other device. MEGAWIN MG84FL54B Data sheet 45 ...
Page 46
... Single Master & Multiple Slaves For the master: can use any port pin, including P2.4 (/SS) to drive the /SS pins of the slaves. For all the slaves: SSIG is ‘0’, and are selected by their corresponding /SS pins. 46 MG84FL54B Data Sheet MEGAWIN ...
Page 47
... Master (idle) 1 input Master (active) 0 Slave output 1 Master input MG84FL54B Data sheet MOSI SPICLK Remarks -pin -pin P2.4~P2.7 are used as input input general port pins. input input Selected as slave. input input Not selected. Mode change to slave if /SS pin is driven low, and ...
Page 48
... Where, Fosc is the system clock. 48 SPI Clock Rate @ Fosc=12MHz 3 MHz 2 MHz 1.5 MHz 1 MHz 750 KHz 500 KHz 250 KHz 125 KHz MG84FL54B Data Sheet Fosc divided MEGAWIN ...
Page 49
... Clock Phase Bit (CPHA) allows the user to set the edges for sampling and changing data. The Clock Polarity bit, CPOL, allows the user to set the clock polarity. The following figures show the different settings of CPHA. 16.3.1. SPI Slave Transfer Format with CPHA=0 16.3.2. SPI Slave Transfer Format with CPHA=1 MEGAWIN MG84FL54B Data sheet 49 ...
Page 50
... SPI Master Transfer Format with CPHA=0 16.3.4. SPI Master Transfer Format with CPHA=1 50 MG84FL54B Data Sheet MEGAWIN ...
Page 51
... And, the TWSI hardware interfaces to the serial bus via two lines: SDA (serial data line, P2.1) and SCL (serial clock line, P2.0). TWSI Bus Interconnection Device 1 SDA SCL MEGAWIN Device 2 Device 3 ..... MG84FL54B Data sheet VCC Pull- Device n 51 ...
Page 52
... P4.3 (SDA) and P4.2 (SCL) may be used as open drain I/O pins. When ENSI is "1", TWSI is enabled, and, the P4.3 and P4.2 port latches must be set to logic 1 for the following serial communication (A3) (A2) (A1 (D4) (D3) (D2 STO SI AA MG84FL54B Data Sheet 1 0 (A0 (D1) (D0 CR1 CR0 MEGAWIN ...
Page 53
... These three bits determine the serial clock frequency when TWSI master mode. The clock rate is not important when TWSI slave mode because TWSI will automatically synchronize with any clock frequency, which is from a master 100KHz. The various serial clock rates are shown in the following table. MEGAWIN MG84FL54B Data sheet 53 ...
Page 54
... START condition as soon as the bus becomes free. When a 54 Serial Clock Rate @ Fosc=12MHz 1.5 MHz 1M KHz 400 KHz 200 KHz 100 KHz 50 KHz 25 KHz 12.5 KHz 4 3 (b4) (b3 STO MG84FL54B Data Sheet Fosc divided 120 240 480 960 (b2) (b1) (b0 CR1 ...
Page 55
... TWSI is switched to the not-addressed slave mode and will ignore the master receiver if it continues the transfer. Thus the master receiver receives all 1s as serial data. While AA is reset, TWSI does not respond to its own MEGAWIN STO MG84FL54B Data sheet CR1 CR0 ...
Page 56
... While AA is reset, TWSI does not respond to its own slave address or a general call address. However, the serial bus is still monitored and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate from the bus. 56 MG84FL54B Data Sheet MEGAWIN ...
Page 57
... To recover from a bus error, the STO flag must be set and SI must be cleared by software. This causes TWSI to enter the “not-addressed” slave mode (a defined state) and to clear the STO flag (no other bits in SICON are affected). The SDA and SCL lines are released (a STOP condition is not transmitted). MEGAWIN MG84FL54B Data sheet 57 ...
Page 58
... The status code in SISTA the current bus state. A START has been transmitted. The bus operation the TWSI has just finished. Setting for the next bus operation. "x" means "don't care" (STA,STO,SI,AA)=(0,0,0,X) SLA+W will be transmitted; The expected next bus operation. ACK bit will be received MG84FL54B Data Sheet MEGAWIN ...
Page 59
... SLA+R will be transmitted; ACK bit will be received; TWSI will be switched to MST/REC mode. A (STA,STO,SI,AA)=(0,0,0,X) To Master/Receiver The bus will be released; Not addressed SLV mode will be entered. MG84FL54B Data sheet From Master/Receiver B (STA,STO,SI,AA)=(1,1,0,X) A STOP followed by a START will be transmitted; STO flag will be reset. Send a STOP ...
Page 60
... ACK will be received; TWSI will be switched to MST/TRX mode. (STA,STO,SI,AA)=(0,0,0,X) The bus will be released; Not addressed SLV mode will be entered. To Master/Transmitter Enter NAslave MG84FL54B Data Sheet C From Slave Mode 40H SLA+R has been transmitted; ACK has been received. (STA,STO,SI,AA)=(0,0,0,1) Data byte will be received; ...
Page 61
... Last data byte will be transmitted; ACK will be received. (STA,STO,SI,AA)=(0,0,0,1) Switch to not addressed SLV mode; Own SLA will be recognized. MG84FL54B Data sheet B8H Data byte in SIDAT has been transmitted; ACK has been received. (STA,STO,SI,AA)=(0,0,0,1) Data byte will be transmitted; ACK will be received. ...
Page 62
... Switch to not addressed SLV mode; No recognition of own SLA; Own SLA will be recognized. A START will be transmitted when the bus becomes free. C MG84FL54B Data Sheet (STA,STO,SI,AA)=(0,0,0,1) Data byte will be received; ACK will be returned. 80H Data byte has been received; ACK has been returned. ...
Page 63
... Switch to not addressed SLV mode; No recognition of own SLA; Own SLA will be recognized. A START will be transmitted when the bus becomes free. C MG84FL54B Data sheet (STA,STO,SI,AA)=(0,0,0,1) Data byte will be received; ACK will be returned. 90H Previously addressed with General Call address; Data byte has been received; ...
Page 64
... WIDL: WDT in Idle mode. Set this bit to let WDT keep counting while the MCU is in the Idle mode. PS2~PS1: Prescaler select. See the following Table. 64 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 8-bit prescalar - ENW WIDL WRF CLRW CLRW WIDL PS2 MG84FL54B Data Sheet 15-bit timer PS2 PS1 PS0 WDTCR Register 1 0 PS1 PS0 MEGAWIN ...
Page 65
... The following Table shows the WDT overflow period for MCU running at 6MHz and 12MHz. The period is the maximum interval for the user to clear the WDT to prevent from chip reset. Table: WDT Overflow Period at Fosc = 6MHz & 12MHz MEGAWIN 15 x (12 x Prescaler / RCosc). MG84FL54B Data sheet 65 ...
Page 66
... WDTCR register ;(because WDTCR is a Write-only register) ;clear buffer for WDTCR register ;@Fosc=6MHz, WDT_Overflow_Period=1.048s ;enable WDT ;clear WDT MG84FL54B Data Sheet Fosc=12MHz 65.536 ms 131.072 ms 262.144 ms 524.288 ms 1.048 s 2.097 s 4.194 s 8.389 s MEGAWIN ...
Page 67
... USB SFR MOVX 2. Ping-Pong Pair MG84FL54B 64B Control 64B INT/BULK 64B INT/BULK/ ISO 64B Total 256B FIFO Total 4 endpoints MG84FL54B Data sheet 1T 8051 Core MG84FL54B 64B Endp 0 64B Endp 1 IN 32B Endp 2 IN 32B 32B Endp 3 OUT 32B Total 256B FIFO ...
Page 68
... EPCON FFE0H FFD8H UADDR IEN FFD0H FFC8H UPCON FFC0H DCON 0/8 1 EN_USB EN_PLL 2/A 3/B 4/C TXSTAT TXDAT TXCON RXSTAT RXDAT RXCON UIE UIFLG UIE1 SIOCTL 2/A 3/B 4/C MG84FL54B Data Sheet PLL_RDY CK_SEL 5/D 6/E 7/F TXCNT RXCNT UIFLG1 5/D 6/E 7/F FFFFH FFF7H FFEFH FFE7H FFDFH FFD7H FFCFH FFC7H MEGAWIN ...
Page 69
... RXD5 RXD4 RXCLR - - RXFFRC - - RXBC6 RXBC5 RXBC4 TXSEQ - - - TXD7 TXD6 TXD5 TXD4 TXCLR - - TXFFRC - - TXBC6 TXBC5 TXBC4 DPI DMI - - MG84FL54B Data sheet Bit-3 Bit-2 Bit-1 Bit-0 EP3DIR - - - UADD3 UADD2 UADD1 UADD0 - URST URSM USUS - EFSR UTXIE1 URXIE0 UTXIE0 - UTXD1 URXD0 UTXD0 - ...
Page 70
... This bit is cleared when firmware writes '1' to it. IEN (Interrupt Enable Register, Address=D9H, SYS_reset=xxxx-x00x, Read/Write Bit7~3: Reserved EP3DIR - UADD4 UADD3 UADD2 URST EFSR MG84FL54B Data Sheet UADD1 UADD0 1 0 FRSM FSUS MEGAWIN ...
Page 71
... Bit2: UTXD1-- USB Transmit Done Flag for endpoint 1. This bit is set by hardware when detected a transmit done on endpoint 1. UC can read/write-clear on this bit. This bit is cleared when firmware writes '1' to it. MEGAWIN UTXIE2 - UTXIE1 UTXD2 - UTXD1 MG84FL54B Data sheet 1 0 URXIE0 UTXIE0 1 0 URXD0 UTXD0 71 ...
Page 72
... Set this bit to enable the double buffer transfer for OUT transaction. Default is cleared. This bit is only valid for endpoint 3 receive mode TXDBM RXISO RXEPEN MG84FL54B Data Sheet 1 0 URXIE3 UTXIE3 URXD3 UTXD3 1 0 EPINX1 EPINX0 1 0 TXISO TXEPEN MEGAWIN ...
Page 73
... When this bit is set, Firmware should write ‘0’ to clear this bit. Bit1~0: Reserved. RXDAT (Receive FIFO Data Register, Endpoint-Indexed, Address=E3H, SYS/USB_reset=xxxx-xxxx, Read-only RXD7 RXD6 RXD5 Bit7~0: RXD[7:0]-- Receive FIFO Data. MEGAWIN EDOVW RXSOVW ISOOVW RXD4 RXD3 RXD2 MG84FL54B Data sheet RXD1 RXD0 73 ...
Page 74
... TXCON (Transmit FIFO Control Register, Endpoint-Indexed, Address=F4H, SYS/USB_reset=0xxx-0xxx, Write- only TXCLR - - Bit7: TXCLR-- Transmit FIFO Clear RXFFRC - RXBC4 RXBC3 RXBC2 TXSOVW - TXD4 TXD3 TXD2 TXFFRC - MG84FL54B Data Sheet RXBC1 RXBC0 TXD1 TXD0 MEGAWIN ...
Page 75
... DPI DMI - Bit7: DPI-- USB DP port state, read only. Read the port status on USB DP. Bit6: DMI-- USB DM port state, read only. Read the port status on USB DM. Bit5~0: Reserved. MEGAWIN TXBC4 TXBC3 TXBC2 MG84FL54B Data sheet 1 0 TXBC1 TXBC0 ...
Page 76
... Software boot select. Set to select booting from ISP-memory, and clear to select booting from AP-memory after software reset. SWRST: Write ‘1’ to trigger software reset. MS2~MS0: ISP mode select, as listed below. MS1 MS0 Byte Program 1 1 Page Erase ISP Mode Standby Read MG84FL54B Data Sheet MS1 MS0 MEGAWIN ...
Page 77
... To do Read Step1: Set [MS1,MS0]=[0,1] in ISPCR register to select Read Mode. Step2: Fill byte address in IFADRH & IFADRL registers. Step3: Sequentially write 0x46 then 0xB9 to SCMD register to trigger an ISP processing. Step4: Now, the Flash data is in IFD register. MEGAWIN MG84FL54B Data sheet 77 ...
Page 78
... IFADRH & IFADRL ; ;trigger ISP processing ; ;[MS1,MS0]=[1,0], select Byte Program Mode ;fill byte address in IFADRH & IFADRL ; ;fill the data to be programmed in IFD ;trigger ISP processing ; ; ;fill byte address in IFADRH & IFADRL ; ;trigger ISP processing ; ;data will be in IFD MG84FL54B Data Sheet MEGAWIN ...
Page 79
... Step3) Update the wanted byte(s) in the buffer. Step4) Program the updated data out of the buffer into this page (using Byte Program mode of ISP). To read the data in the IAP-memory, users can use either the “MOVC A,@A+DPTR” instruction or the Read mode of ISP. MEGAWIN MG84FL54B Data sheet 79 ...
Page 80
... Fosc (System Clock 48MHz PLL To USB Logic XCKS[4:0] CKS[2:0] CK_SEL 4 3 XCKS1 XCKS0 CLKin default CLKin /2 CLKin /4 CLKin /8 CLKin /16 CLKin /32 CLKin /64 CLKin /128 MG84FL54B Data Sheet CKS2 CKS1 CKS0 MEGAWIN ...
Page 81
... XTAL oscillating. And, after MCU successfully runs up, the user can program the bit to some values that can keep XTAL oscillating stable. Refer to the following table for the values. OSCDR0 0 1 MEGAWIN EN_USB XTAL ranges Up to 32MHz(TBD) Down to 1MHz(TBD) MG84FL54B Data sheet EN_PLL PLL_RDY CK_SEL 81 ...
Page 82
... POF is set to “1” by hardware during power up (i.e., cold start) or when VCC power drops below the POR voltage. It can be set or reset under software control and is not affected by any warm reset such as RST-pin reset, software reset (ISPCR.5) and WDT reset. Note that it should be cleared by software POF GF1 GF0 MG84FL54B Data Sheet IDL MEGAWIN ...
Page 83
... OR2 (Option Register 2) MEGAWIN HWBS HWBS2 ISP-memory Size ISP Start Address 4K bytes 3.5K bytes 3K bytes 2.5K bytes 2K bytes 1.5K bytes 1K bytes (No ISP space is configured IAPLB MG84FL54B Data sheet LOCK 0x3000 0x3200 0x3400 0x3600 0x3800 0x3A00 0x3C00 - ...
Page 84
... If HWWIDL and HWPS[2:0] are programmed and 5, respectively, then WDTCR will be initialized to be 0x2D when MCU is powered up, as shown below. 1 (disabled): No action on Watch-dog Timer when MCU powered up PSEN - - HWWIDL HWPS2 MG84FL54B Data Sheet HWPS1 HWPS0 MEGAWIN ...
Page 85
... Signed 8-bit offset byte. Used by SJMP and all conditional jumps. Range is –128 to +127 bytes rel relative to first byte of the following instruction. bit 128 direct bit-addressable bits in internal RAM, any I/O pin, control or status bit. MEGAWIN MG84FL54B Data sheet 85 ...
Page 86
... DEC A Decrement ACC DEC Rn Decrement register DEC direct Decrement direct byte DEC @Ri Decrement indirect RAM MUL AB Multiply A and B DIV AB Divide Decimal Adjust ACC 86 MG84FL54B Data Sheet Execution Byte Clock Cycles ...
Page 87
... RL A Rotate ACC Left RLC A Rotate ACC Left through the Carry RR A Rotate ACC Right RRC A Rotate ACC Right through the Carry SWAP A Swap nibbles within the ACC MEGAWIN MG84FL54B Data sheet Execution Byte Clock Cycles ...
Page 88
... Note1:If EXTRAM=1, all “MOVX” instructions are used for the external data memory accessing. And, if EXTRAM=0, all “MOVX” instructions are directed to the on-chip XRAM (if address= 0x0000~0x0FFF) and USB SFRs (if address = 0xFFC0~0xFFFF). Note2: The cycle time for access of external data memory is (ALE_Stretched_Clocks) + (RW_Stretched_Clocks) 88 MG84FL54B Data Sheet Execution Byte Clock Cycles 1 1 ...
Page 89
... AND complement of direct bit to Carry ORL C,bit OR direct bit to Carry ORL C,/bit OR complement of direct bit to Carry MOV C,bit Move direct bit to Carry MOV bit,C Move Carry to direct bit MEGAWIN MG84FL54B Data sheet Execution Byte Clock Cycles ...
Page 90
... Compare immediate data to register and jump if not equal 3 Compare immediate data to indirect RAM and jump if not CJNE @Ri,#data,rel DJNZ Rn,rel Decrement register and jump if not equal DJNZ direct,rel Decrement direct byte and jump if not equal NOP No operation 90 l MG84FL54B Data Sheet Execution Byte Clock Cycles ...
Page 91
... PIN V = 2.4V 64 PIN V = 0.45V 7 PIN V = 0.45V 0 PIN = V 0 PIN 1.4V 100 PIN F = 12MHz 9 OSC F = 12MHz 3.5 OSC VDD_IO= 3.3V 0.1 VDD_IO= 3.3V 160 MG84FL54B Data sheet Unit °C ° Unit max 500 150 Kohm ...
Page 92
... V Differential Input Sensitivity DI V Differential Input Common Mode Range CM I Input Leakage current L 92 Test min Condition 2.8 1 1.425 – 0.2 0.8 Pull-up Disabled MG84FL54B Data Sheet Limits Unit typ max V 0 ohm 44 ohm 1.5 1.575 Kohm 2.5 V <1.0 uA MEGAWIN ...
Page 93
... Field Applications Home Appliance Healthcare POS Control Wireless Dongle Joy Stick Wireless Keyboard/Mouse 29. Order Information Part Number MG84FL54BD 30. Package Dimension MG84FL54BD (LQFP-48) MEGAWIN Temperature Range Package LQFP-48 -40℃~85℃ MG84FL54B Data sheet Packing Operation Voltage Tray 3.3V 93 ...
Page 94
... V0.98 2008/01 94 Page Description - Initial public data sheet. P95,96 - Add maximum rating and Electrical Characteristics Extend flash data retention from 7 to 100 years. P9,10 - Add T2CKO on P10. P91 - Modify R max/min value in Dc Table RST P95,96 - Finalize Electrical Characteristics. MG84FL54B Data Sheet . MEGAWIN ...