mpc82g516a Megawin Technology, mpc82g516a Datasheet - Page 104

• Manufacturer Part Number: mpc82g516a
• Description: 8-bit Microcontroller
• Manufacturer: Megawin Technology

20.2.4 Notes for ISP
Developing of the ISP Code
Although the ISP code is programmed in the ISP-memory that has an ISP Start Address in the MCU’s Flash (see
Figure 20-1), it doesn’t mean you need to put this offset (= ISP Start Address) in your source code. The code
offset is automatically manipulated by the hardware. You just needs to develop it like you develop your
application program in the AP-memory.
Interrupts during ISP
After triggering the ISP processing, the MCU will halt for a while for internal ISP processing until the processing is
completed. At this time, the interrupt will queue up for being serviced if the interrupt is enabled previously. Once
the processing is completed, the MPU continues running and the interrupts in the queue will be serviced
immediately if the interrupt flag is still active. The user, however, should be aware of the following:
(1) Any interrupt can not be in-time serviced when the MCU halts for ISP processing.
(2) The low-level triggered external interrupts, /INTx, should keep activated until the ISP is completed, or they
will be neglected.
Accessing Destination of ISP
As mentioned previously, the ISP is used to program both the AP-memory and the IAP-memory. Once the
accessing destination address is beyond that of the last byte of the IAP-memory, the hardware will automatically
neglect the triggering of ISP processing. That is the triggering of ISP is invalid and the hardware does nothing.
Flash Endurance for ISP
The endurance of the embedded Flash is 20,000 erase/write cycles, that is to say, the erase-then-write cycles
shouldn’t exceed 20,000 times. Thus the user should pay attention to it in the application which needs to
frequently update the AP-memory and IAP-memory.
Flash Write Protection during Low Power
To ensure a successful programming using ISP, the power coming from LDO output and supplied to the Flash
memory should be higher than 2.4V (see Figure 23-1). The user may enable the hardware option LVFWP for
write protection during the LDO output power falls below 2.4V during ISP processing. Refer to
Section 25: MCU’s
Hardware
Option.
MPC82G516A Data Sheet
104
MEGAWIN