mpc82g516a Megawin Technology, mpc82g516a Datasheet - Page 74

• Manufacturer Part Number: mpc82g516a
• Description: 8-bit Microcontroller
• Manufacturer: Megawin Technology

SPCTL (Address=85H, SPI Control Register, Reset Value=0000,0100B)
SSIG: /SS is ignored
SPEN: SPI enable
DORD: SPI data order
MSTR: Master/Slave mode select
CPOL: SPI clock polarity select
CPHA: SPI clock phase select
SPR1-SPR0: SPI clock rate select (in master mode)
SPSTAT (Address=84H, SPI Status Register, Reset Value=00xx,xxxxB)
SPIF: SPI transfer completion flag
When a serial transfer finishes, the SPIF bit is set and an interrupt is generated if SPI interrupt is enabled. If /SS
pin is driven low when SPI is in master mode with SSIG=0, SPIF will also be set to signal the “mode change”.
The SPIF is cleared in software by writing ‘1’ to this bit.
WCOL: SPI write collision flag.
The WCOL bit is set if the SPI data register, SPDAT, is written during a data transfer (see
Collision). The WCOL flag is cleared in software by writing ‘1’ to this bit.
SPDAT (Address=86H, SPI Data Register, Reset Value=0000,0000B)
SPDAT has two physical buffers for writing to and reading from during transmit and receive, respectively.
MEGAWIN
(MSB)
SSIG
SPIF
7
7
7
If SSIG=1, MSTR decides whether the device is a master or slave.
If SSIG=0, the /SS pin decides whether the device is a master or slave.
If SPEN=1, the SPI is enabled.
If SPEN=0, the SPI interface is disabled and all SPI pins will be general-purpose I/O ports.
1 : The LSB of the data byte is transmitted first.
0 : The MSB of the data byte is transmitted first.
1: SPICLK is high when Idle. The leading edge of SPICLK is the falling edge and the trailing edge is
0: SPICLK is low when Idle. The leading edge of SPICLK is the rising edge and the trailing edge is
1: Data is driven on the leading edge of SPICLK, and is sampled on the trailing edge.
0: Data is driven when /SS pin is low (SSIG=0) and changes on the trailing edge of SPICLK. Data is
00 : Fosc/4
01 : Fosc/16
10 : Fosc/64
11 : Fosc/128 (
sampled on the leading edge of SPICLK.
(Note : If SSIG=1, CPHA must not be 1, otherwise the operation is not defined.)
SPEN
the rising edge.
the falling edge.
WCOL
6
6
6
DORD
5
5
Where, Fosc is the system clock.)
5
-
MSTR
4
4
4
-
CPOL
MPC82G516A Data Sheet
3
3
3
-
CPHA
2
2
2
-
SPR1
1
1
1
-
SPR0
(LSB)
0
0
0
-
Section 15.6: Write
74