mpc82g516a Megawin Technology, mpc82g516a Datasheet - Page 56

• Manufacturer Part Number: mpc82g516a
• Description: 8-bit Microcontroller
• Manufacturer: Megawin Technology

false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the
frame will proceed.
As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the
shift register (which in mode 1 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and
RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following
conditions are met at the time the final shift pulse is generated:
1. RI = 0, and
2. Either SM2 = 0, or the received stop bit = 1.
If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the
stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether the above
conditions are met or not, the unit goes back to looking for a 1-to-0 transition at the RXD input.
12.1.7 More About Modes 2 and 3
11 bits are transmitted through TXD, or received through RXD: a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of 0
or 1. On receive, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64
the system clock frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1 or Timer 2.
Figure 12-3 and Figure 12-4 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is
exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift
register.
Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal
also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a
transmission is requested. Transmission commences at the instruction cycle following the next rollover in the
divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the “write to SBUF”
signal.)
The transmission begins with activation of Send, which puts the start bit at TXD. One bit time later, data is
activated, which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit
time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only
zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at
the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that
contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate Send and set TI.
This occurs at the 11th divide-by-16 rollover after “write to SUBF.”
Reception is initiated by a detected 1-to-0 transition at RXD. For this purpose RXD is sampled at a rate of 16
times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is
immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th, and 9th counter states of each bit
time, the bit detector samples the value of RXD. The value accepted is the value that was seen in at least 2 of the
3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes
back to looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register,
and reception of the rest of the frame will proceed.
As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the
shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load
SBUF and RB8, and set RI.
The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met
at the time the final shift pulse is generated.
1. RI = 0, and
2. Either SM2 = 0, or the received 9th data bit = 1.
If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions
are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later,
whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RXD
input.
MPC82G516A Data Sheet
56
MEGAWIN