MPC89L51A Megawin Technology, MPC89L51A Datasheet
MPC89L51A
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MPC89L51A Summary of contents
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... In-Application Program ............................................................................................... 31 Note for Other SFR...................................................................................................... 32 Absolute Maximum Rating (MPC89E51A) ........................................................................ 33 DC Characteristics (MPC89E51A)...................................................................................... 33 Absolute Maximum Rating (MPC89L51A) ........................................................................ 34 DC Characteristics (MPC89L51A)...................................................................................... 34 Package Dimension.............................................................................................................. 35 Revision History .................................................................................................................. 38 This document contains information on a new product under development by Megawin. Megawin reserves the right to change or discontinue this product without notice. © ...
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... The data endurance of the embedded flash gets over 20,000 times. - Greater than 100 years data rentention under room temperature Operating Voltage: www.DataSheet4U.com - 4.5V~5.5V for MPC89E51A - 2.4V~3.6V for MPC89L51A, minimum 2.7V requirement in flash write operation (ISP/ICP/…...) - Built-in Low-Voltage-Reset circuit. Operating Temperature - Industrial (-40°C to +85°C)* Maximum Operating Frequency: ...
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General Description MPC89x51A is a single-chip 8-bits micro-controller with the instruction sets fully compatible with industrial-standard 80C51 series microcontroller. There is 4 Kbytes flash memory embedded for application program, 11 Kbytes data flash shared by In-System Programming code, and In-Application-Programming ...
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Pin Description Pin Definition Pin Name DIP-40 P0.0 (AD0) 39 P0.1 (AD1) 38 P0.2 (AD2) 37 P0.3 (AD3) 36 P0.4 (AD4) 35 P0.5 (AD5) 34 P0.6 (AD6) 33 P0.7 (AD7) 32 P1.0 (T2) 1 P1.1 (T2EX) 2 P1.2 3 P1.3 ...
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P3.5 (T1) 15 P3.6 (/WR) 16 P3.7 (/RD) 17 P4.0 P4.1 P4.2 (/INT3) P4.3 (/INT2) RESET 9 ALE 30 /PSEN 29 www.DataSheet4U.com /EA 31 XTAL1 19 XTAL2 18 VDD 40 VSS 20 MEGAWIN keep the port high. Port3 also serves ...
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Pin Configuration 1 (T2) P1.0 (T2EX) P1.1 2 P1.2 3 P1.3 4 P1.4 5 P1 P1.7 RESET 9 (RXD) P3.0 10 (TXD) P3.1 11 (INT0) P3.2 12 (INT1) P3.3 13 (T0) P3 (/WR) ...
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Block Diagram B Register www.DataSheet4U.com PSEN ALE EA RESET XTAL1 MEGAWIN P2.0 ~ P2.7 Port2 Driver RAM ADDR Port2 Latch RAM256 Register ACC TMP2 TMP1 ALU PSW WDT Port1 Latch Port3 Latch Control Unit Port1 Driver Port3 Driver XTAL2 P1.0 ...
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Special Function Register ACC WDTCR D8 D0 PSW C8 T2CON T2MOD C0 XICON B8 IP SADEN SADDR SCON SBUF TCON TMOD 80 P0 SYMBOL ...
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Memory Organization www.DataSheet4U.com Address Space for MPC89x51A embedded Flash memory Bits-7 Bits FZWDTCR MEGAWIN 00-7F RAM, Access it via direct addressing 80-FF SFR, Access it via direct addressing 80-FF indirect on-chip RAM, Access it via indirect addressing 00-FF ...
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Nonvolatile Registers: There are two Nonvolatile Registers named OR0 and OR1 individually. They are designed to configure the MPC89x51A options. Generally these two nonvolatile registers will be written via a popular NVM writer, say Hi-Lo System All-11, Leaper-48 and Megawin-Provided ...
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NVM register: OR1 (Option Register 1): Bits-7 Bits-6 FZWDTCR FZWDTCR: Used to freeze the WDT-controlling register. 0:= Configure the SFR WDTCR to be reset only via power-up action; not by software reset nor reset from the Watch Dog Timer. 1:= ...
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Embedded Flash There is totally 15 K bytes flash embedded in the MPC89x51A. The leading 4 K bytes flash memory is designed for storage of the user program, followed 11 K bytes flash memory is shared with nonvolatile data flash ...
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Functional Description TIMERS/COUNTERS MPC89x51A has three 16-bits timers, and they are named T0, T1 and T2.Each of them can also be used as a general event counter, which counts the transition from While T0/T1/T2 is used as ...
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SFR: TCON Bits-7 Bits-6 TF1 TR1 TF1: =Timer1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to the interrupt routine, or clearing the bits in software. TR1: =Timer1 run control bits. Set/Cleared by ...
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C/T2: Timer or counter select for timer and 1 is for external event counter. CP/RL2: Capture/Reload flag. When set, captures will occurs on a negative transition at T2EX if EXEN2=1. When cleared, auto-reloads will occur either with Timer2 ...
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OSC/ pin 1 (Sampled) C//T GATE /INTx Mode 3 Timer1 in Mode3 simply holds its count, the effect is the same as setting TR1 = 1. Timer0 in Mode 3 enables TL0 and TH0 as two ...
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Timer2 is also can be configured as a periodical signal generator. The MPC89x51A is able to generate a programmable clock output on P1.0. When T2OE bits is set and C//T2 bits is cleared, Timer2 overflow pulse will generate a 50% ...
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Auto-Reload Up-Only Mode (ARUO) In ARUO mode, Timer2 can be configured to count up with a software-defined value to be reloaded. When reset is applied to the DCEN =0 and CP/RL2=0, Timer2 is at ARUO mode. An overflow on Timer2 ...
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Baud-Rate Generator Mode (BRG) Timer2 can be configured to generate various baud-rate. Bits TCLK and/or RCLK in T2CON allow the serial port transmit and receive baud rates to be derived from either Timer1 or Timer2. When TCLK=0, Timer1 is used ...
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Interrupt There are eight interrupt sources available in MPC89x51A. Each interrupt source can be individually enabled or disabled by setting or clearing a bits in the SFR named IE. This register also contains a global disable bits (EA), which can ...
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In other words, interrupts or pending interrupts can be generated or canceled in software. The following content describes several SFR related to interrupt mechanism. SFR: IE (Interrupt Enabling): Bits-7 Bits-6 EA EA: Global disables ...
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IP (or XICON) and IPH are combined to form 4-level priority interrupt as the following table. {IPH.x , IP. SFR: XICON (External Interrupt Control): Bits-7 Bits-6 PX3 EX3 PX3: If set, Set priority for external interrupt ...
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SFR: WDTCR (Watchdog Timer Control): Bits-7 Bits ENW: Enable WDT while it is set. ENW cannot be cleared by firmware enable watchdog timer does not use watchdog timer CLRW: Clear WDT to recount while ...
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Mode2 An 11-bits data is serially transmitted through TXD or received through RXD. The frame data includes a start bits (0), 8 data bits, a programmable data bits comes from TB8 in SFR SCON. On receive, the ...
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SM2: Enable the automatic address recognition feature in mode 2 and 3. If SM2=1, RI will not be set unless th the received 9 data bits is 1, indicating an address, and the received bytes is a Given or Broadcast ...
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In other words, not all data reception will respond to RI, while specific data does. By setting the SADDR and the SADEN, the user can filter out those data bytes that doesn’t like to care. This feature brings great help ...
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POWER-DOWN mode The user can set the bits PCON.1 to drive this chip entering POWER-DOWN mode. In the POWER-DOWN mode, the on-chip oscillator is stopped. The contents of on-chip RAM and SFRs are maintained. The power-down mode can be ...
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MPC89x51A carried with convenient mechanism to help the user read/change the flash content. Just filling the target address and data into several SFR, and triggering the built-in ISP automation, the user can easily erase, read, and program the embedded flash ...
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Bits-7 Bits-6 SCMD is the command port for triggering ISP activity. If SCMD is filled with sequential 46h, B9h and if ISPCR ISP activity will be triggered. When this register is read, the device ID of MPC89x51A will ...
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IFMT ← xxxxx010 ISPCR ← 100xx010 IFADRH ← (Address high byte) IFADRL ← (Address low byte) IFD ← (byte date to be written into flash) SCMD ← 46h SCMD ← B9h (CPU progressing will be hold here) (CPU continues) IFMT ...
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SWBS 0, and trigger a software reset. After that, the system will be reset (not powered-up), and the system will refer to SWBS to startup from AP program entrance. For power-up procedure, the HWBS will ...
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Note for Other SFR SFR: AUXR Bits-7 Bits ERAM: Define if hide the expanded RAM access to the external RAM 0: = The internal auxiliary RAM access is enabled 1: =The internal auxiliary RAM access is ...
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Absolute Maximum Rating Parameter Ambient temperature under bias Storage temperature Voltage on any Port I/O Pin or RST with respect to Ground Voltage on VCC with respect to Ground Maximum total current through VCC and Ground Maximum output current sunk ...
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... I Logic transition current (P1,2,3, Operating current @20MHz CC I Idle mode current @ 20MHz IDLE I Power down current PD Rrst Internal pull-down resistance in RESET 34 (MPC89L51A) (MPC89L51A) Parameter Test Condition Vcc=3.3V Vcc=3.3V (RESET) Vcc =3.3V Vcc=3.3V (RESET) Vcc=3.3V Vcc=3.3V Vcc = 3.3V Vcc =3.3V Vpin=0V Vpin=2.0V Vcc=3.3V Vcc=3.3V Vcc=3 ...
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Package Dimension 40-pin PDIP (MPC89x51AE) www.DataSheet4U.com MEGAWIN MPC89x51A Data Sheet 35 ...
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PLCC (MPC89x51AP) www.DataSheet4U.com 36 MPC89x51A Data Sheet MEGAWIN ...
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PQFP (MPC89x51AF) www.DataSheet4U.com MEGAWIN MPC89x51A Data Sheet 37 ...
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Revision History Version Date A3 2004/10 A4 2004/11 P27 A5 2005/01 A6 2005/3/ 2005/6/14 P5 2006/08 P33 2007/03 P34 A10 2007/12 P2 A11 2008/12 www.DataSheet4U.com 38 Page - reorganized - Added Procedures demonstrating ...