mg87fel04 Megawin Technology, mg87fel04 Datasheet
mg87fel04
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... WDT Register ..................................................................................................................... 32 14. Reset.......................................................................................................... 34 14.1. Reset Source ...................................................................................................................... 34 15. Power Management ................................................................................... 35 This document contains information on a new product under development by MEGAWIN. MEGAWIN reserves the right to change or discontinue this product without notice. © MEGAWIN Technology Co., Ltd. 2009 All rights reserved. Preliminary MG87FE/L04 8-bit micro-controller 2010/01. version 1.04 ...
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Power Saving Mode............................................................................................................ 35 15.1.1. Idle Mode...................................................................................................................... 35 15.1.2. Power-down Mode ....................................................................................................... 35 15.1.3. Interrupt Recovery from Power-down........................................................................... 35 15.1.4. Reset Recovery from Power-down............................................................................... 36 15.1.5. GPIO wake-up Recovery from Power-down................................................................. 36 15.2. Power Control Register....................................................................................................... 36 16. System ...
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General Description MG87FE/L04 is single-chip 8-bits microcontroller with the instruction sets fully compatible with industrial-standard 80C51 series embedded to provide widely field application. In-System-Programming and In-Application-Programming allows the users to download new code or data while the microcontroller sits ...
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Features 80C51 Central Processing Unit MG87FE/L04 with 4KB flash ROM Operating voltage: 4.5V~5.5V for MG87FE04 ; 2.7V ~ 3.6V for MG87FL04. Operation frequency : Internal RC-oscillator (default 22.118MHz@12T） with +/- 4% frequency drift @ -40 ~ 85℃ IAP capability; ...
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Block Diagram RAM ADDR Register Port4 Latch Int. OSC RST Logic RESET WDT MEGAWIN RAM256 PWM Timer Timer0/1 8051 Core Interrupt Port1 Latch Port3 Latch + - Port1 Driver Port3 Driver P1.0~P1.1 P1.3 P1.5 P3.0 ~ P3.2 MG87FE/L04 Data ...
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Pin Configurations 4.1. Package Instruction 6 MG87FE/L04 Data Sheet MEGAWIN ...
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Pin Description (MSOP-10) Pin Name Pin-Number I/O type P1.0, P1. P1.3, P1.5 10, 1 P3.0~P3.2, 4~6, (P3.6) RESET 3 VDD 2 VSS 7 MEGAWIN Port1: General-purposed I/O with weak pull-up resistance inside. I/O When 1s are written ...
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CPU Function Description 5.1. CPU Register PSW: Program Status Word Address=D0H, read/write, Power On + RESET=0000-0000 CY: Carry bit. AC: Auxiliary carry bit. F0: General purpose flag 0. RS1: Register bank select ...
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CPU Timing A machine cycle is the shortest timing period to achieve an instruction. In MG87FE/L04, some instructions need 1 machine cycle to achieve, but others need machine cycles. A machine cycle takes 12 clock periods ...
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Memory Organization MG87FE/L04 device has separate address spaces for program and data memory. On-chip data memory can be accessed by 8-bit addresses, which can be quickly stored and manipulated by the 8-bit CPU. Program memory in MG87FE/L04 can only ...
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On-Chip Data RAM 30H Bit addressable 20H Bank3 1FH Bank2 10H Bank1 08H Bank0 00H MG87FE/L04 has internal data RAM that is mapped into three separate segments. They are lower 128 bytes of RAM, upper 128 bytes of RAM ...
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Special Function Register 7.1. SFR Map 0/8 1/9 F8H B F0H 00000000 P4 E8H XXXX11XX ACC WDTCR E0H 00000000 0X000000 CCON CMOD D8H 00XXXXXX 00000000 PSW D0H 00000000 C8H XICON C0H 00000000 IPL SADEN B8H XXX00000 00000000 P3 B0H ...
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SFR Bit Assignment SYMBOL DESCRIPTION ADDRESS SP Stack Pointer DPL Data Pointer Low DPH Data Pointer High PCON Power Control TCON Timer Control TMOD Timer Mode TL0 Timer Low 0 TL1 Timer Low 1 TH0 Timer High 0 TH1 ...
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Note1: The registers are addressed by IFMT and SCMD. Please refer the IFMT register description for more detail information. 14 MG87FE/L04 Data Sheet MEGAWIN ...
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Configurable I/O Ports 8.1. IO Structure 8.1.1. Port 1/3/4 GPIO Structure Port latch data By the way, the pull-up resistor is disabled on P10/P11 in default. 8.2. Port1 Register P1: Port 1 Register Address=90H, read/write, Power On + RESET=1111-1111 ...
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Port4 Register P4: Port 4 Register Address=E8H, read/write, Power On + RESET=XXXX-11XX Bit 7~4: Reserved. Bit 3: P4.3 could be set / cleared by program. Bit 2: Must always set to 1. Bit ...
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Interrupt 9.1. Interrupt Structure TCON.IT0 /INT0 TCON.TF0 TCON.TF1 SCON.RI SCON.TI XICON.IT2 /INT2 0 1 AUXR.INT2H ACSR.ACF CCON.CF MEGAWIN Global Enable IPL,IPH,XICON (IE.EA) Registers IE.EX0 IE0 IE.ET0 IE.ET1 IE.ES XICON.EX2 IE2 0 1 IE.EAC 0 1 CMOD.ECF MG87FE/L04 Data sheet ...
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Interrupt Register IE: Interrupt Enable Register Address=E8H, read/write, Power On + RESET=00X0-0000 EAC -- Bit 7: EA, All interrupts enable register. 0: Global disables all interrupts. 1: Global enables all interrupts. Bit 6: EAC, Analog ...
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Cleared when interrupt start to be serviced. It also could be cleared by CPU. 1: Set by hardware when external interrupt edge detected. It also could be set by CPU. Bit 0: IT2, Interrupt 2 type control bit. 0: ...
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Source External interrupt 0 Timer 0 -- Timer1 Serial Port -- External interrupt 2 or Comparator PWM-Timer The external interrupt /INT0, and /INT2 can each be either level-activated or transition-activated, depending on bits IT0 in register TCON, IT2 in register ...
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Timers/Counters MG87FE/L04 has two Timers/Counters: Timer 0 and Timer 1. All of them can be configured as timers or event counters. (Due to no pin out /INT1 & T0 (10-pin package) in MG87FE/L04, T0 count & /INT1 GATE (10-pin ...
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Mode 2 operation is the same for Timer0 and Timer1. 10.1.4. Mode 3 Structure Timer1 in Mode3 simply holds its count, the effect is the same as setting TR1 = 1. Timer0 in Mode 3 enables TL0 and TH0 ...
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Timer0/1 Register TMOD: Timer/Counter Mode Control Register Address=89H, read/write, Power On + RESET=0000-0000 GATE C ----------------------- Timer1 ------------------------- | --------------------------Timer0 ------------------------ | Bit 7/3: Gate, Gating control for Timer1/0. 0: Disable gating control for ...
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PWM-Timer An 8-bits timer that special designed for PWM generator. 10.2.1. PWM-Timer Structure Pre-Scaler / System Clock /8 /16 /32 /64 /128 IDLE CIDL CF 10.2.2. PWM-Timer Register 24 CCAP0H CCAP0L CL 8-bit Down Counter POS2 POS1 ...
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CMOD: PWM-timer Mode Register Address=D9H, read/write, Power On + RESET=0000-0000 CIDL POS2 POS1 Bit 7: CIDL, Counter Idle Control. 0: Program the PWM-Timer to continue functioning during IDLE mode. 1: Program the PWM-Timer to be gated off ...
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CCAP0H: PWM-Timer H-Duty Register Address=FAH, read/write, Power On + RESET=0000-0000 MG87FE/L04 Data Sheet MEGAWIN ...
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UART The serial port (UART) of MG87FE/L04 support full-duplex transmission. It can transmit and receive simultaneously. The serial port receive and transmit share the same SFR – SBUF, but actually there is two SBUFs in the chip, one is ...
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This feature is enabled by setting the SM2 bit in SCON. In mode2 and mode3, the receive interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address ...
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Bit 2: RB8, In Modes 2 and 3, the 9 was received. In Mode 0, RB8 is not used. Bit 1: TI. Transmit interrupt flag. 0: Must be cleared by software. 1: Set by hardware at the end of the ...
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Analog Comparator A single analog comparator is provided in the MG87FE/L04. The comparator operation is such that the output is a logical “HIGH” when the positive input AIN0 (P1.0]) is greater than the negative input AIN1 (P1.1). Otherwise the ...
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Bit 7: ACIDX, Analog Comparator IDLE control. 0: Program the Analog Comparator to be gated off during IDLE mode. 1: Program the Analog Comparator to continue functioning during IDLE mode. Bit 6~5: Reserved. Bit 4: ACF. Analog Comparator Interrupt Flag. ...
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Watch Dog Timer (WDT) 13.1. WDT Structure Fosc IDLE 13.2. WDT Register WDTCR: Watch-Dog-Timer Control Register Address=E1H, read/write, Power On + Reset =0x00-0000 WRF - ENW Bit 7: WRF, WDT reset flag. 0: This bit should ...
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Bit 2~0: PS2 ~ PS0, select pre-scalar output for WDT time base input. PS[2: MEGAWIN Pre-scalar ...
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Reset During reset, all I/O Registers are set to their initial values, the port pins are weakly pulled to VDD, and the program starts execution from the Reset Vector, 0000H, or ISP start address by OR setting. MG87FE/L04 all ...
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Power Management MG87FE/L04 supports two power-reducing modes: Idle and Power-down mode. These two modes are accessed through the PCON register. 15.1. Power Saving Mode 15.1.1. Idle Mode Setting the IDL bit in PCON enters idle mode. Idle mode halts ...
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When PWDEX = 1 the wake-up period is controlled externally by the interrupt. Again, at the falling edge on the interrupt pin, Power-down is exited and the oscillator is restarted. However, the internal clock will not propagate and CPU will ...
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Bit 3~2: GF1, GF0, General purpose flags. Bit 1: PD, Power-Down control bit. 0: This bit could be cleared by CPU or any exited power-down event. 1: Setting this bit activates power down operation. Bit 0: IDL, Idle mode control ...
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System Clock 16.1. Clock Structure 16.2. Clock Register CKCON: Clock Control Register Address=C7H, read/write, RESET=xxxx-x000 Bit 7~3: Reserved. Bit 2~0: SCKS2 ~ SCKS0, programmable System Clock Selection. SCKS[2: ...
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The driving of crystal oscillator is reduced. It will helpful in EMI reduction. Regarding application not needing high frequency clock recommended to do so. Bit 6: EN6TR, Enable 6T mode control register. affect CKCON3.EN6TR to corre ...
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In System Programming (ISP) IFD: ISP/IAP Flash Data Register Address=E2H, read/write, RESET=1111-1111 IFD is the data port register for ISP/IAP operation. The data in IFD will be written into the desired address in operating ISP/IAP write ...
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The IAPLB content has already finished the updated sequence. The range of the IAP-memory is determined by IAPLB and the ISP start address as listed below. IAP lower boundary = IAPLBx256, and IAP higher boundary = ISP start address – ...
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In Application Programming (IAP) MG87FE/L04 available program memory size (AP-memory) is restricted to 4K. The flash memory between IAPLB and ISP start address could be defined as data flash memory and can be accessed by the ISP operation in ...
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Auxiliary SFRs AUXR: Auxiliary Control Register Address=8EH, read/write, RESET=0000-0000 INT2H P15FS Bit 7: Reserved. Must clear Bit 6: INT2H, INT2 High/Rising trigger enable. 0: Remain INT2 triggered on low level or falling ...
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Absolute Maximum Rating For MG87FE/L04 Parameter Ambient temperature under bias Storage temperature Voltage on any Port I/O Pin or RESET with respect to Ground Voltage on VDD with respect to Ground Maximum total current through VDD and Ground Maximum ...
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Electrical Characteristics 21.1. DC Characteristics VSS = 0V ℃ VDD = 5.0V and 12 clocks per machine cycle, unless otherwise specified , Symbol Parameter V Input High voltage (Ports IH1 V Input High ...
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Package Dimension MSOP-10 46 MG87FE/L04 Data Sheet MEGAWIN ...
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Instruction Set MNEMONIC DATA TRASFER MOV A,Rn Move register to Acc MOV A, direct Move direct byte o Acc MOV A,@Ri Move indirect RAM to Acc MOV A,#data Move immediate data to Acc MOV Rn,A Move Acc to register ...
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INC A Increment Acc INC Rn Increment register INC direct Increment direct byte INC @Ri Increment indirect RAM DEC A Decrement Acc DEC Rn Decrement register DEC direct Decrement direct byte DEC @Ri Decrement indirect RAM INC DPTR Increment DPTR ...
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MOV C,bit Move direct bit to Carry MOV bit,C Move Carry to direct bit JC rel Jump if Carry is set JNC rel Jump if Carry not set BOOLEAN VARIABLE MANIPULATION JB bit,rel Jump if direct bit is set JNB ...
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Revision History Version Date V1.00 2009/Sep./16 V1.01 2009/OCT/23 V1.02 2009/OCT/27 V1.03 2009/NOV/16 V1.04 2010/JAN/12 50 Page - Initial release - change package type &change 87E04 as 87FE/L04 - IC part number changed as MG87FE/L04 part number ...