mc68hc908bd48 Freescale Semiconductor, Inc, mc68hc908bd48 Datasheet - Page 259

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mc68hc908bd48

Manufacturer Part Number
mc68hc908bd48
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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19.4 I/O Signals
19.4.1 OSCXCLK
19.4.2 STOP Instruction
19.4.3 COPCTL Write
19.4.4 Power-On Reset
MC68HC908BD48
Freescale Semiconductor
NOTE:
Rev. 2.1
A COP reset pulls the RST pin low for 32 OSCXCLK cycles and sets the
COP bit in the SIM reset status register (SRSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ1 is held
at V
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
The following paragraphs describe the signals shown in
OSCXCLK is the crystal oscillator output signal. OSCXCLK frequency is
equal to the crystal frequency.
The STOP instruction clears the COP prescaler.
Writing any value to the COP control register (COPCTL)
Control
of the prescaler. Reading the COP control register returns the low byte
of the reset vector.
The power-on reset (POR) circuit clears the COP prescaler 4096
OSCXCLK cycles after power-up.
TST
. During the break state, V
Computer Operating Properly (COP)
Register) clears the COP counter and clears bits 12 through 5
TST
on the RST pin disables the COP.
Computer Operating Properly (COP)
(see 19.5 COP
Figure
Data Sheet
19-1.
259

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