mc68hc908bd48 Freescale Semiconductor, Inc, mc68hc908bd48 Datasheet - Page 220

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mc68hc908bd48

Manufacturer Part Number
mc68hc908bd48
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Sync Processor
Data Sheet
220
COINV — Clamp Output Invert
SOGSEL —þ SOG Select
CLAMPOE —þClamp Output Enable
BPOR — Back Porch
SOUT — Sync Output Enable
This bit is set to invert the clamp pulse output to negative. Reset
clears this bit.
This bit selects either the HSYNC pin or SOG pin as the composite
sync signal input pin. Reset clears this bit.
This bit is set to enable the clamp pulse output circuitry. Reset clears
this bit.
This bit defines the triggering edge of the clamp pulse output relative
to the HSYNC input. Reset clears this bit.
This bit will select the output signals for the VSYNCO and HSYNCO
pins. Reset clears this bit.
1 = clamp output is set for negative pulses
0 = clamp output is set for positive pulses
1 = SOG pin is used as the composite sync input
0 = HSYNC pin is used as the composite sync input
1 = Clamp pulse circuit enabled
0 = Clamp pulse circuit disabled
1 = Clamp pulse is generated on the trailing edge of HSYNC
0 = Clamp pulse is generated on the leading edge of HSYNC
1 = VSYNCO and HSYNCO outputs are internally generated
0 = VSYNCO and HSYNCO outputs are processed VSYNC and
free-running sync pulses with frequencies determined by
HVCOR[2:0] bits in HVCOR.
HSYNC inputs respectively
Sync Processor
MC68HC908BD48
Freescale Semiconductor
Rev. 2.1

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