mc68hc908bd48 Freescale Semiconductor, Inc, mc68hc908bd48 Datasheet - Page 226

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mc68hc908bd48

Manufacturer Part Number
mc68hc908bd48
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Sync Processor
16.6.6 H&V Sync Output Control Register (HVOCR)
Data Sheet
226
Address:
ATPOL — Auto Polarity
FSHF — Fast Horizontal Frequency Count
Reset:
Read:
Write:
This bit, together with the VINVO or HINVO bits in SPCSR controls
the output polarity of the VSYNCO or HSYNCO signals respectively.
Reset clears this bit (see
This bit is set to shorten the measurement cycle of the horizontal
frequency. If it is set, only HFH[7:0] and HFL[4:2] will be updated by
the Hsync counter, providing a count in a 8ms window in every
8.192ms, with HFL[1:0] reading as zeros. Therefore, user can
determine the horizontal frequency change within 8.192ms to protect
critical circuitry. Reset clears this bit.
Figure 16-10. H&V Sync Output Control Register (HVOCR)
ATPOL
1 = Number of Hsync pulses is counted in an 8ms window
0 = Number of Hsync pulses is counted in a 32ms window
0
0
1
1
$0047
Bit 7
R
0
Table 16-9. ATPOL, VINVO, and HINVO setting
= Unimplemented
Sync Processor
6
0
0
VINVO / HINVO
0
1
0
1
5
0
0
Table
4
0
0
16-9).
Same polarity as sync input
Inverted polarity of sync input
Negative polarity sync output
Positive polarity sync output
R
3
0
0
VSYNCO/HSYNCO
Sync Outputs:
MC68HC908BD48
HVOCR2 HVOCR1 HVOCR0
= Reserved
Freescale Semiconductor
2
0
1
0
Rev. 2.1
Bit 0
0

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