ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 41

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

Figure 2–26. EP1SGX25F Device Inter-Transceiver & Global Clock Connections
Notes to
(1)
(2)
(3)
Altera Corporation
June 2006
IQ lines are inter-transceiver block lines.
If the /2 pre-divider is used, the path to drive the PLD logic array, local, or global clocks is not allowed.
There are four receiver PLLs in each transceiver block.
Figure
IQ0
2–26:
IQ1
IQ2
Global Clocks, I/O Bus, General Routing
Global Clocks, I/O Bus, General Routing
Global Clocks, I/O Bus, General Routing
Global Clocks, I/O Bus, General Routing
Global Clocks, I/O Bus, General Routing
Global Clocks, I/O Bus, General Routing
Global Clocks, I/O Bus, General Routing
Global Clocks, I/O Bus, General Routing
Transceiver Block 0
Transceiver Block 1
Transceiver Block 2
Transceiver Block 3
refclkb
refclkb
refclkb
refclkb
IQ0
IQ1
IQ2
IQ0
IQ1
IQ2
IQ0
IQ1
IQ2
IQ0
IQ1
IQ2
/2
/2
/2
/2
Transmitter
Transmitter
Transmitter
Transmitter
PLL
PLL
PLL
PLL
Receiver
Receiver
Receiver
Receiver
PLLs
PLLs
PLLs
PLLs
4
4
4
4
Stratix GX Device Handbook, Volume 1
(2)
(2)
(2)
4
4
4
4
Note (1)
Stratix GX Transceivers
16
PLD Global Clocks
2–31