ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 108

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ep1sgx25d

Manufacturer Part Number
ep1sgx25d
Description
Stratix Gx Device Family Data Sheet
Manufacturer
Altera Corporation
Datasheet

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TriMatrix Memory
4–42
Stratix GX Device Handbook, Volume 1
Input/Output Clock Mode
Input/output clock mode can be implemented for both the true and
simple dual-port memory modes. On each of the two ports, A or B, one
clock controls all registers for inputs into the memory block: data input,
wren, and address. The other clock controls the block’s data output
registers. Each memory block port, A or B, also supports independent
clock enables and asynchronous clear signals for input and output
registers.
clock mode.
Figures 4–24
and
4–25
show the memory block in input/output
Altera Corporation
February 2005

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