ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 134
ep1sgx25d
Manufacturer Part Number
ep1sgx25d
Description
Stratix Gx Device Family Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP1SGX25D.pdf
(272 pages)
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PLLs & Clock Networks
PLLs & Clock
Networks
4–68
Stratix GX Device Handbook, Volume 1
clock signals are routed from LAB row clocks and are generated from
specific LAB rows at the DSP block interface. The LAB row source for
control signals, data inputs, and outputs is shown in
Stratix GX devices provide a hierarchical clock structure and multiple
PLLs with advanced features. The large number of clocking resources in
combination with the clock synthesis precision provided by enhanced
and fast PLLs provides a complete clock management solution.
Stratix GX devices contain up to four enhanced PLLs and up to four fast
PLLs. In addition, there are four receiver PLLs and one transmitter PLL
per transceiver block located on the right side of Stratix GX devices.
Global & Hierarchical Clocking
Stratix GX devices provide 16 dedicated global clock networks,
16 regional clock networks (four per device quadrant), 8 dedicated fast
regional clock networks within EP1SGX10 and EP1SGX25, and 16
dedicated fast regional clock networks within EP1SGX40 devices.
1
2
3
4
5
6
7
8
Table 4–16. DSP Block Signal Sources & Destinations
LAB Row at
Interface
signa
aclr0
accum_sload0
addnsub1
clock0
ena0
aclr1
clock1
ena1
aclr2
clock2
ena2
sign_b
clock3
ena3
clear3
accum_sload1
addnsub3
Control Signals
Generated
A1[17..0]
B1[17..0]
A2[17..0]
B2[17..0]
A3[17..0]
B3[17..0]
A4[17..0]
B4[17..0]
Data Inputs
Table
Altera Corporation
OA[17..0]
OB[17..0]
OC[17..0]
OD[17..0]
OE[17..0]
OF[17..0]
OG[17..0]
OH[17..0]
Data Outputs
February 2005
4–16.
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