ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 142

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

PLLs & Clock Networks
Figure 4–47. EP1SGX40 Device I/O Clock Groups
4–76
Stratix GX Device Handbook, Volume 1
IO_CLKM[7:0]
IO_CLKO[7:0]
IO_CLKN[7:0]
IO_CLKP[7:0]
8
8
8
8
IO_CLKA[7:0]
22 Clocks in the
22 Clocks in the
Half-Quadrant
Half-Quadrant
8
You can use the Quartus II software to control whether a clock input pin
is either global, regional, or fast regional. The Quartus II software
automatically selects the clocking resources if not specified.
Enhanced & Fast PLLs
Stratix GX devices provide robust clock management and synthesis using
up to four enhanced PLLs and four fast PLLs. These PLLs increase
performance and provide advanced clock interfacing and clock frequency
synthesis. With features such as clock switchover, spread spectrum
IO_CLKL[7:0]
8
IO_CLKB[7:0]
22 Clocks in the
22 Clocks in the
Half-Quadrant
Half-Quadrant
8
IO_CLKK[7:0]
8
IO_CLKC[7:0]
22 Clocks in the
22 Clocks in the
Half-Quadrant
Half-Quadrant
8
IO_CLKJ[7:0]
8
IO_CLKD[7:0]
22 Clocks in the
22 Clocks in the
Half-Quadrant
Half-Quadrant
8
IO_CLKI[7:0]
8
Altera Corporation
February 2005
I/O Clock Regions
13
14
17
16
15