ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 140

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

PLLs & Clock Networks
Figure 4–45. Regional Clock Bus
4–74
Stratix GX Device Handbook, Volume 1
Fast Regional Clock Network [1..0]
Regional Clock Network [3..0]
Global Clock Network [15..0]
IOE clocks have horizontal and vertical block regions that are clocked by
eight I/O clock signals chosen from the 22-quadrant or half-quadrant
clock resources.
quadrant relationship to the I/O clock regions, respectively. The vertical
regions (column pins) have less clock delay than the horizontal regions
(row pins).
Figures 4–46
or Half-Quadrant
Clocks Available
to a Quadrant
Clock [21:0]
and
4–47
show the quadrant and half-
Vertical I/O Cell
IO_CLK[7..0]
Lab Row Clock [7..0]
Horizontal I/O
Cell IO_CLK[7..0]
Altera Corporation
February 2005