ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 110

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

TriMatrix Memory
Figure 4–25. Input/Output Clock Mode in Simple Dual-Port Mode
Note to
(1)
4–44
Stratix GX Device Handbook, Volume 1
All registers shown except the rden register have asynchronous clear ports.
Figure
wraddress[ ]
address[ ]
byteena[ ]
outclken
wrclock
inclken
rdclock
data[ ]
wren
rden
4–25:
8 LAB Row
Clocks
8
Read/Write Clock Mode
The memory blocks implement read/write clock mode for simple dual-
port memory. You can use up to two clocks in this mode. The write clock
controls the block’s data inputs, wraddress, and wren. The read clock
controls the data output, rdaddress, and rden. The memory blocks
support independent clock enables for each clock and asynchronous clear
signals for the read- and write-side registers.
memory block in read/write clock mode.
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
Q
Q
Q
Q
Q
Q
Generator
Pulse
Write
Data In
Read Address
Byte Enable
Write Address
Read Enable
Write Enable
Memory Block
Data Out
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
256 ´ 16
512 ´ 8
Note (1)
D
ENA
Figure 4–26
Q
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