ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 267

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
June 2006
t
f
f
t
t
t
t
t
t
t
f
FCOMP
OUT
OUT_EXT
OUTDUTY
JITTER
CONFIG5,6
CONFIG11,12
SCANCLK
DLOCK
LOCK
VCO
Table 6–90. Enhanced PLL Specifications for -7 Speed Grade (Part 2 of 3)
Symbol
External feedback clock compensation
time
Output frequency for internal global or
regional clock
Output frequency for external clock
Duty cycle for external clock output
(when set to 50%)
Period jitter for external clock output
Time required to reconfigure the scan
chains for PLLs 5 and 6
Time required to reconfigure the scan
chains for PLLs 11 and 12
scanclk frequency
Time required to lock dynamically (after
switchover or reconfiguring any non-
post-scale counters/delays)
Time required to lock from end of
device configuration
PLL internal VCO operating range
(3)
Parameter
(4)
(10)
(6) (10)
(2)
(5)
Min
300
0.3
0.3
(8)
45
10
Typ
Stratix GX Device Handbook, Volume 1
±20 mUI for <200 MHz outclk
±100 ps for >200 MHz outclk
DC & Switching Characteristics
289/f
193/f
600
Max
420
434
100
400
55
SCANCLK
SCANCLK
22
6
(7)
ps or
MHz
MHz
MHz
MHz
Unit
mUI
6–65
ns
μs
μs
%