ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 77

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Figure 4–17. Cyclone III Input/Output Clock Mode in Single-Port Mode
Note to
(1)
Altera Corporation-Preliminary
March 2007
addressstall
outclocken
address[ ]
byteena[ ]
inclocken
outclock
inclock
data[ ]
See the Cyclone III Device Family Data Sheet in the Cyclone III Device Handbook, Volume 1, for more information on the
MultiTrack interconnect.
wren
rden
Figure
6 LAB Row
Clocks
6
4–17:
Read/Write Clock Mode
Cyclone III M9K memory blocks can implement read/write clock mode
for FIFO and simple dual-port memories. In this mode, a write clock
controls the data inputs, write address, and write-enable registers.
Similarly, a read clock controls the data outputs, read address, and read-
enable registers. The memory blocks support independent clock enables
for both the read and write clocks.
read/write clock mode.
D
ENA
D
ENA
D
ENA
D
ENA
ENA
D
Q
Q
Q
Q
Q
Read Enable
Data In
Address
Byte Enable
Address
Clock Enable
Write Enable
Memory Block
Figure 4–18
Cyclone III Device Handbook, Volume 1
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
256 ´ 16
512 ´ 8
Data Out
shows memory block in
D
ENA
Q
Clocking Modes
To MultiTrack
Interconnect (1)
4–23