ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 18
ep3c120f780c8nes
Manufacturer Part Number
ep3c120f780c8nes
Description
Cyclone Iii Device Family
Manufacturer
Altera Corporation
Datasheet
1.EP3C120F780C8NES.pdf
(582 pages)
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Cyclone III Device Family Overview
1–2
Cyclone III Device Handbook, Volume 1
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Highest multiplier-to- logic ratio in the industry at every density;
260 MHz multiplier performance
High I/O count, low and mid range density devices for user I/O
constrained applications
Up to four phase-locked loops (PLLs) provide robust clock
management and synthesis for device clocks, external system clocks,
and I/O interfaces
●
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Support for high-speed external memory interfaces including DDR,
DDR2, SDR SDRAM, and QDRII SRAM at up to 400 Mbps
●
Up to 534 user I/O pins arranged in 8 I/O banks that support a wide
range of industry I/O standards
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Multi-value on-chip termination (OCT) support with calibration
feature to eliminate variations over PVT
Adjustable I/O slew rates to improve signal integrity
Support for low-cost Altera serial flash and commodity parallel flash
configuration devices from Intel and Spansion
Remote system upgrade feature without requiring an external
controller
Dedicated Cyclic Redundancy Code (CRC) checker circuitry to
detect single event upset (SEU) conditions
Nios
and custom-fit embedded processing solutions
Broad portfolio of pre-built and verified intellectual property cores
from Altera and Altera Megafunction Partners Program (AMPP
partners
Up to five outputs per PLL
Cascadable to save I/Os, ease PCB routing, and reduce the
number of external reference clocks needed
Dynamically reconfigurable to change phase shift, frequency
multiplication/division, and input frequency in-system without
reconfiguring the device
Auto-calibrating physical layer (PHY) feature accelerates timing
closure process and eliminates variations over process, voltage
and temperature (PVT) for DDR, DDR2, SDRAM, and QDRII
SRAM interfaces
Up to 875 Mbps receive and 840 Mbps transmit LVDS
communications
LVDS, RSDS, mini-LVDS and PPDS transmission without the
use of external resistors
Supported I/O standards include LVTTL, LVCMOS, SSTL,
HSTL, PCI, PCI-X, LVPECL, LVDS, mini-LVDS, RSDS, and
PPDS; PCI Express and Serial Rapid I/O are supported using
external PHY devices
®
II embedded processors for Cyclone III devices offer low cost
Altera Corporation-Preliminary
March 2007
SM
)
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