ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 190

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Cyclone III Device I/O Features
Conclusion
Document
Revision History
7–38
Cyclone III Device Handbook, Volume 1
March 2007 v1.0
Table 7–13. Document Revision History
Document
Date and
Version
f
Initial Release
Σ I
pin
There is a current limit of 240 mA per 14 consecutive output side pins (left
and right) per power pair, as shown by the following equation:
pin+13
Σ I
pin
1
For more information about Cyclone III FPGAs power estimation, refer
to The Power Play III Early Power Estimator User Guide for Cyclone III
FPGAs.
Cyclone III device I/O capabilities enable you to keep pace with
increasing design complexity utilizing a low-cost FPGA device family.
Support for various I/O standard compatibility allow Cyclone III devices
to fit into a wide variety of applications. Quartus II software makes it easy
to use these I/O standards in Cyclone III device designs.
After design compilation, the software also provides clear, visual
representations of pads and pins and the selected I/O standards. Taking
advantage of the support of these I/O standards in Cyclone III devices
allows you to lower your design costs without compromising design
flexibility or complexity.
Table 7–13
PIN
PIN
< 240 mA per power pair
< 240 mA per power pair
In all the cases listed above, the Quartus II software generates an
error message for illegally placed pads. The I
programmable current strength and is the same as the current
strength as set in the Quartus II software.
shows the revision history for this document.
Changes Made
Altera Corporation-Preliminary
Summary of Changes
PIN
varies with
March 2007