ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 278

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Configuring Cyclone III Devices
10–42
Cyclone III Device Handbook, Volume 1
1
As shown in
CONF_DONE pins on all target devices are connected together with
external pull-up resistors. These pins are open-drain bidirectional pins on
the devices. When the first device asserts nCEO (after receiving all of its
configuration data), it releases its CONF_DONE pin. However, the
subsequent devices in the chain keep this shared CONF_DONE line low
until they have received their configuration data. When all target devices
in the chain have received their configuration data and have released
CONF_DONE, the pull-up resistor drives a high level on this line and all
devices simultaneously enter initialization mode.
If an error occurs at any point during configuration, the nSTATUS line is
driven low by the failing device. If you enable the Auto-restart
configuration after error option, reconfiguration of the entire chain begins
after a reset time-out period (a maximum of 80 s). If the Auto-restart
configuration after error option is turned off, the external system must
monitor nSTATUS for errors and then pulse nCONFIG low to restart
configuration. The external system can pulse nCONFIG if it is under
system control rather than tied to V
Configuring With Multiple Bus Masters
Similar to AS configuration scheme, AP configuration scheme supports
multiple bus masters for the parallel flash. For another master to take
control of the AP configuration bus, it must assert nCONFIG low for at
least 500 ns to reset the master Cyclone III device and over-ride the weak
10 kΩ pull-down resistor on the nCE pin. This resets the master
Cyclone III device and causes it to tri-state its AP configuration bus. The
other master then takes control of the AP configuration bus. Once the
other master is done, it must release the AP configuration bus, then
release the nCE pin, and finally pulse nCONFIG low to restart
reconfiguration.
In the AP configuration scheme, multiple masters can share the parallel
flash. Similar to the AS configuration scheme, the bus control is
negotiated by the nCE pin. The AP configuration with multiple bus
masters is shown in
In multi-device AP configuration, the board trace length
between the parallel flash to the master Cyclone III device
should be within maximum of 6 inches. Additionally, you must
connect the repeater buffers between the Cyclone III master and
slave device(s) for DATA[15..0] and DCLK. All I/O inputs
must maintain a maximum AC voltage of 4.1 V. The output
resistance of the repeater buffers has to fit the maximum
overshoot equation outlined in
I/O Requirements” on page
Figure 10–10
Figure
and
10–12.
Figure
CCIO
10–13.
10–11, the nSTATUS and
.
“Configuration and JTAG Pin
Altera Corporation-Preliminary
March 2007