ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 427

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Cyclone III Device Datasheet: DC & Switching Characteristics
Altera Corporation-Preliminary
March 2007
Notes to
(1)
(2)
(3)
(4)
(5)
f
t
f
clock output)
f
clock)
t
t
t
t
f
t
t
f
EINDUTY
INJITTER
OUT_EXT
OUT
OUTDUTY
LOCK
DLOCK
t
t
PLL_PSERR
VCO
ARESET
CONFIGPLL
SCANCLK
Table 1–19. Cyclone III PLL Specifications
OU TJIT TE R_DEDCLK
OU TJIT TE R_IO
(to global
This parameter is limited in Quartus II software by the I/O maximum frequency. The maximum I/O frequency is
different for each I/O standard.
For extended temperature devices, the maximum lock time is 500 us.
With 100 MHz scanclk frequency.
Pending silicon characterization.
V
Symbol
CCD_PLL
(external
Table
(1)
should always be connected to V
1–19:
External feedback clock input duty cycle
Input clock period jitter
PLL output frequency (-6 speed grade)
PLL output frequency (-7 speed grade)
PLL output frequency (-8 speed grade)
PLL output frequency (-6 speed grade)
PLL output frequency (-7 speed grade)
PLL output frequency (-8 speed grade)
Duty cycle for external clock output (when
set to 50%)
Time required to lock from end of device
configuration
Time required to lock dynamically (after
switchover or reconfiguring any non-post-
scale counters/delays)
Dedicated clock output period jitter
Regular I/O period jitter
Accuracy of PLL phase shift
PLL internal VCO operating range
Minimum pulse width on areset signal.
Time required to reconfigure scan chains
for PLLs
scanclk frequency
Parameter
CCINT
(5)
through decoupling capacitor and ferrite bead.
(Part 2 of 2)
Min
600
45
10
5
5
5
5
5
5
3.5
100
Typ
(3)
Cyclone III Handbook
100
100
472.5
402.5
1300
Max
450
300
±60
100
(4)
(4)
(4)
55
(4)
(2)
(2)
Preliminary
SCANCLK
cycles
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ps
us
ps
ps
ps
ns
%
%
1–17