ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 165

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Altera Corporation-Preliminary
March 2007
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1
Refer to the Assignment Editor chapter in volume 2 of the Quartus II
Handbook for more information about how to set the programable pull-
up resistor.
Programmable Delay
The Cyclone III device IOE includes programmable delays to ensure zero
hold times, minimize setup times, or increase clock-to-output times.
A path in which a pin directly drives a register may require a
programmable delay to ensure zero hold time, whereas a path in which a
pin drives a register through combinational logic may not require the
delay. Programmable delays minimize setup time. The Quartus II
Compiler can program these delays to automatically minimize setup time
while providing a zero hold time. Programmable delays can increase the
register-to-pin delays for output registers.
programmable delays for Cyclone III devices.
There are two paths in the IOE for an input to reach the logic array. Each
of the two paths can have a different delay. This allows you to adjust
delays from the pin to the internal LE registers that reside in two different
areas of the device. You set the two combinational input delays by using
the Input delay from pin to internal cells logic option in the Quartus II
software for each path. If the pin uses the input register, one of delays is
disregarded and the delay is set by using the Input delay from pin to
input register logic option in the Quartus II software.
The IOE registers in each I/O block share the same source for the preset
or clear features. You can program preset or clear for each individual IOE,
but you cannot use both features simultaneously. You can also program
the registers to power-up high or low after configuration is complete. If
programmed to power-up low, an asynchronous clear can control the
registers. If programmed to power-up high, an asynchronous preset can
Input pin to logic array delay
Input pin to input register delay
Output pin delay
Table 7–2. Cyclone III Programmable Delay Chain
Programmable Delays
If you enable the programmable pull-up, the device cannot use
the bus-hold feature. The programmable pull-up resistors are
not supported on the dedicated configuration, Joint Test Action
Group (JTAG), and dedicated clock pins.
Cyclone III Device Handbook, Volume 1
Delay from output register to output pin
Input delay from pin to internal cells
Input delay from pin to input register
Table 7–2
Quartus II Logic Option
shows the
I/O Element Features
7–13