dac1408d650 NXP Semiconductors, dac1408d650 Datasheet - Page 53

• Manufacturer Part Number: dac1408d650
• Description: Dual 14-bit Dac, Up To 650 Msps, 2? And 4? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1408D650_1
Objective data sheet
Table 69.
Default settings are shown highlighted.
Table 70.
Table 71.
Bit
7 to 4 MAN_LOCK_LN1[3:0] R/W
3 to 0 MAN_LOCK_LN0[3:0] R/W
Bit
7 to 4 MAN_LOCK_LN3[3:0] R/W
3 to 0 MAN_LOCK_LN2[3:0] R/W
Bit
7
6
5
4
3
2
0
1
Symbol
WORD_SWAP_LN3
WORD_SWAP_LN2
WORD_SWAP_LN1
WORD_SWAP_LN0
SELECT_RF_F10_LN3
SELECT_RF_F10_LN2
SELECT_RF_F10_LN1
SELECT_RF_F10_LN0
Symbol
Symbol
MAN_LOCK_LN_1_0 register (address 03h) bit description
MAN_LOCK_2_0 register (address 04h) bit description
CA_CNTRL register (address 05h) bit description
Rev. 01 — 26 May 2009
Access Value Description
Access Value Description
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Access Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
manual lock-settting sync-word-alignment lane_3
manual lock-settting sync-word-alignment lane_2
manual lock-settting sync-word-alignment lane_1
manual lock-settting sync-word-alignment lane_0
Description
dout_ca_ln3[7:0] = din_ca_ln3[7:0]
dout_ca_ln3[7:0] = din_ca_ln3[0:7]
dout_ca_ln2[7:0] = din_ca_ln2[7:0]
dout_ca_ln2[7:0] = din_ca_ln2[0:7]
dout_ca_ln1[7:0] = din_ca_ln1[7:0]
dout_ca_ln1[7:0] = din_ca_ln1[0:7]
dout_ca_ln0[7:0] = din_ca_ln0[7:0]
dout_ca_ln0[7:0] = din_ca_ln0[0:7]
din_ca_ln3 sampled @ falling edge f10_ln3
din_ca_ln3 sampled @ rising edge f10_ln3
din_ca_ln2 sampled @ falling edge f10_ln2
din_ca_ln2 sampled @ rising edge f10_ln2
din_ca_ln1 sampled @ falling edge f10_ln1
din_ca_ln1 sampled @ rising edge f10_ln1
din_ca_ln0 sampled @ falling edge f10_ln0
din_ca_ln0 sampled @ rising edge f10_ln0
DAC1408D650
© NXP B.V. 2009. All rights reserved.
53 of 88