dac1408d650 NXP Semiconductors, dac1408d650 Datasheet - Page 29
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dac1408d650
Manufacturer Part Number
dac1408d650
Description
Dual 14-bit Dac, Up To 650 Msps, 2? And 4? Interpolating With Jesd204a Interface
Manufacturer
NXP Semiconductors
Datasheet
1.DAC1408D650.pdf
(88 pages)
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NXP Semiconductors
DAC1408D650_1
Objective data sheet
10.11 Analog output
(register 0Ch; see
register 0Eh; see
the range of variation of the digital offset (see
Table 16.
Default settings are shown highlighted.
The DAC1408D650 has two output channels each of which produces two complementary
current outputs. These allow the even-order harmonics and noise to be reduced. The pins
are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected via a
load resistor R
For the equivalent analog output circuit of one DAC, refer to
output circuit (one
sources, and their associated switches, for each segment.
The cascode source configuration increases the output impedance of the source, thus
improving the dynamic performance of the DAC by introducing less distortion.
The device can provide an output level of up to 2 V
following stages and the targeted performances.
DAC_OFFSET[11:0]
Decimal
...
0
+1
...
2046
2047
Fig 14. Equivalent analog output circuit (one DAC)
2048
2047
1
Digital offset adjustment
L
to the 3.3 V analog power supply (V
Table 33 “DAC_B_CFG_3 register (address 0Eh) bit
Table 31 “DAC_B_CFG_1 register (address 0Ch) bit description”
DAC)”. This circuit consists of a parallel combination of NMOS current
Rev. 01 — 26 May 2009
AGND
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Two’s complement
1000 0000 0000
1000 0000 0001
...
1111 1111 1111
0000 0000 0000
0000 0000 0001
...
0111 1111 1110
0111 1111 1111
AGND
Table 16 “Digital offset
IOUTAP/IOUTBP
IOUTAN/IOUTBN
o(p-p)
DDA(3V3)
depending on the application, the
DAC1408D650
).
Figure 14 “Equivalent analog
Offset applied
...
0
+2
...
+4092
+4094
V
4096
4094
2
DDA(3V3)
R L
001aah019
R L
adjustment”).
description”) define
© NXP B.V. 2009. All rights reserved.
29 of 88
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