dac1408d650 NXP Semiconductors, dac1408d650 Datasheet - Page 45

• Manufacturer Part Number: dac1408d650
• Description: Dual 14-bit Dac, Up To 650 Msps, 2? And 4? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1408D650_1
Objective data sheet
Table 42.
Default settings are shown highlighted.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Bit
7
6
5
4
3
2
1
0
Bit
7 to 0 RST_EXT_FCLK[7:0]
Bit
7 to 0 RST_EXT_DCLK[7:0] R/W
Bit
7 to 0 DCSMU_PREDIVCNT[7:0]
Bit
7 to 0 PLL_CHARGE_TIME[7:0]
Bit
7 to 0 PLL_RUNIN_TIME[7:0] R/W
Bit
7 to 0 CA_RUNIN_TIME[7:0] R/W
Symbol
Symbol
MAN_PLL_SEL_PD_LN3
MAN_PLL_SEL_PD_LN2
MAN_PLL_SEL_PD_LN1
MAN_PLL_SEL_PD_LN0
MAN_PLL_STARTUP_LN3
MAN_PLL_STARTUP_LN2
MAN_PLL_STARTUP_LN1
MAN_PLL_STARTUP_LN0
Symbol
Symbol
Symbol
Symbol
Symbol
MAN_SUPD register (address 02h) bit description
RST_EXT_FCLK register (address 04h) bit description
RST_EXT_DCLK register (address 05h) bit description
DCSMU_PREDIVCNT register (address 06h) bit description
PLL_CHARGETIME register (address 07h) bit description
PLL_RUN_IN_TIME register (address 08h) bit description
CA_RUN_IN_TIME register (address 09h) bit description
Rev. 01 — 26 May 2009
Access Value Description
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Access Value Description
Access Value Description
R/W
Access Value Description
Access Value Description
R/W
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access Value Description
R/W
20h
04h
3Fh
32h
32h
1Eh
specifies extension-time reset_dclk (in
dclk-periods)
Value Description
clock alignment run in time (at f
specifies extension-time reset_fclk in f
periods
PLL run in time (at f
PLL chargetime (at f
value used by dcsmu predivider (at f
sel_pd_ln3 (when man_supd_cntrl = 1)
sel_pd_ln2 (when man_supd_cntrl = 1)
sel_pd_ln1 (when man_supd_cntrl = 1)
sel_pd_ln0 (when man_supd_cntrl = 1)
startup_ln3 (when man_supd_cntrl = 1)
startup_ln2 (when man_supd_cntrl = 1)
startup_ln1 (when man_supd_cntrl = 1)
startup_ln0 (when man_supd_cntrl = 1)
DAC1408D650
clk
/predivcnt; sel_pd)
clk
/predivcnt; startup)
© NXP B.V. 2009. All rights reserved.
clk
/predivcnt)
clk
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clk
)