dac1408d650 NXP Semiconductors, dac1408d650 Datasheet - Page 15

• Manufacturer Part Number: dac1408d650
• Description: Dual 14-bit Dac, Up To 650 Msps, 2? And 4? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1408D650_1
Objective data sheet
Fig 3.
SYNC_OUT
lane#
The descrambler can be enabled/disabled
JESD204A receiver
DES
10.2.1 Lane input
10.2 JESD204A receiver
10b
The JEDEC204A defines the following parameters:
The DAC1408D650 supports both LMF = 421 and LMF = 211. The current setting is
configurable via the SPI registers interface.
The complete Digital Layer Processing adds a variable delay on each lane path. This is
mainly due to the inter-lane alignment.
Table 6.
[1]
[2]
Each lane is CML compliant. It is terminated to a common voltage with an integrated 50
resistor.
Symbol Parameter
t
d
CLOCK
ALIGN
frame
clock
Frame clock cycle
D = guaranteed by design.
10b
delay time
Digital Layer Processing Latency
L is the number of lanes per link,
M is the number of converters per device,
F is the number of bytes per frame clock period,
WORD
ALIGN
SYNC
AND
Conditions
Digital Layer Processing
delay
10b
Rev. 01 — 26 May 2009
K-DETECT
10b/8b
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
RX CONTROLLER
8b
DESCRAMBLER
Test
D
[2]
8b
Min
13
DAC1408D650
Typ
-
8b
8b
8b
8b
© NXP B.V. 2009. All rights reserved.
Max
28
14b
14b
configuration
interface
internal
001aak161
Unit
Cycle
15 of 88
[1]