dac1408d650 NXP Semiconductors, dac1408d650 Datasheet - Page 16

• Manufacturer Part Number: dac1408d650
• Description: Dual 14-bit Dac, Up To 650 Msps, 2? And 4? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1408D650_1
Objective data sheet
Fig 5.
data in +
data in
DC coupling
10.2.2 Sync & word align
50
The common mode voltage is programmable. See
map”
DC coupling is only possible if both DAC and transmitter have the same common mode
voltage. Else, AC coupling is required.
The deserializer performs the incoming data clock recovery and also the serial to parallel
conversion. Therefore, each lane includes its own PLL that must first lock.
Then the clock alignment module transfers the data from the re-generated clock to the
frame clock domain. The frequency of both clocks are the same but the phase relation
between the clocks isn’t known.
As stated in JESD204A, transmitter and receiver have to first synchronize. This is
achieved through SYNC_OUT signals and SYNC pattern (K28.5 symbol).
The receiver (i.e. DAC1408D650) first drives its SYNC outputs. The SYNC signal/pattern
is continuously sent until the receiver deasserts the SYNC signal.
The Lane Processing makes use of the SYNC-patterns to synchronize the datastream,
determine the initial running disparity and to extract the 10 bits word from the incoming
datastream (word-alignment).
Fig 4.
50
for register value.
Zdiff = 100
Lane input termination
50
001aak162
50
Rev. 01 — 26 May 2009
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Vin_p
Vin_n
Fig 6.
data in +
data in
50
50
AC coupling
Vtt
Ztt
001aak166
Table 39 “Page 2 register allocation
V
50
DD1
50
DAC1408D650
Zdiff = 100
© NXP B.V. 2009. All rights reserved.
V
50
DD2
001aak163
50
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