pi7c8154a Pericom Semiconductor Corporation, pi7c8154a Datasheet - Page 87

• Manufacturer Part Number: pi7c8154a
• Description: 2-port Pci-to-pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

14.1.32
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h
Bit
26
27
31:28
Bit
0
1
2
3
Function
Broken Master
Timeout Enable
Automatic
Preemption
Control
Reserved
Function
Memory Read
Flow Through
Disable
Park
Downstream (P
to S) Memory
Read Dynamic
Prefetching
Upstream (S to
P) Memory Read
Dynamic
Prefetching
Type
R/W
R/W
R/O
Type
R/W
R/W
R/W
R/W
Page 87 of 112
Description
0: Broken master timeout off. If a master receives its GNT# active but
does not initiate any transactions for more than 16 clocks, the arbiter will
consider the master as broken for only two clocks. The current GNT# will
be de-asserted if another master asserts its REQ# or automatic preemption
is on (bit[27] offset 40h); otherwise the current GNT# will be kept
asserted.
1: Broken master timeout on. If a master receives its GNT# active but
does not initiate any transactions for more than 16 clocks, the arbiter will
consider the master as broken and the REQ# of the current master will be
ignored for arbitration until de-assertion of its REQ#. The current GNT#
will be de-asserted if another master asserts its REQ# or automatic
preemption is on (bit[27] offset 40h); otherwise the current GNT# will be
kept asserted.
Reset to 0
0: Automatic preemption off. If the preemption timer expires
(bit[31:28] offset 4Ch) and another master asserts REQ#, the GNT# of
the current master will be de-asserted and the GNT# of the next master
will be asserted. If no other master asserts REQ#, the current GNT# will
remain asserted.
1: Automatic preemption on. If the preemption timer expires
(bit[31:28] offset 4Ch), the GNT# to the current master will be de-
asserted for one clock. The same GNT# will be asserted again if no other
master asserts its REQ#. If another master asserts its REQ#, the arbiter
will generate a GNT# for the next master with the highest priority.
Reset to 0
Returns 0000 when read. Reset to 0000.
Description
Controls ability to do memory read flow through
0: Enable flow through during a memory read transaction
1: Disables flow through during a memory read transaction
Reset to 0
Controls bus arbiter’s park function
0: Park to last master
1: Park to the bridge
Reset to 0
0: Enable downstream memory read prefetching dynamic control
1: Disable downstream memory read prefetching dynamic control
Reset to 0
0: Enable upstream memory read prefetching dynamic control
1: Disable upstream memory read prefetching dynamic control
Reset to 0
ASYNCHRONOUS 2-PORT
JULY 2004 REVISION 1.00
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A