pi7c8154a Pericom Semiconductor Corporation, pi7c8154a Datasheet - Page 36
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pi7c8154a
Manufacturer Part Number
pi7c8154a
Description
2-port Pci-to-pci Bridge
Manufacturer
Pericom Semiconductor Corporation
Datasheet
1.PI7C8154A.pdf
(112 pages)
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2.9.4
2.9.5
For write transactions, PI7C8154A redirects the write data that it has on the AD[63:32] bus to
AD[31:0] during the second data phase if it does not detect ACK64# asserted at the same time that
it detects DEVSEL# asserted. Also, the CBE[7:4] is redirected to CBE[3:0] during the second data
phase.
For 64-bit memory write transactions that end at an odd DWORD boundary, PI7C8154A drives the
byte enable bits to 1 during the last data phase. AD[63:32] are then unpredictable but are driven to
a valid logic level.
For read transactions, PI7C8154A drives 8 bits of byte enables on CBE[7:0] when it has asserted
REQ64#. CBE[7:0] is always 0 because the only read transactions that use the 64-bit extension are
prefetchable memory reads. No special redirection is needed based on the target’s assertion or lack
of assertion of ACK64#. When the target asserts ACK64# at the same time that it asserts
DEVSEL#, all read data transfers consist of 64 bits and the target asserts PAR64, which covers
AD[63:32] and CBE[7:4]. All data phase consist of 32-bit transactions when the target does not
assert ACK64# and asserts DEVSEL#.
64-BIT TRANSACTIONS – RECEIVED BY PI7C8154A
PI7C8154A does one of 2 things when it is the target of a transaction and REQ64# is asserted.
PI7C8154A either asserts ACK64# at the same time it asserts DEVSEL# to indicate its ability to
perform 64-bit data transfers, or it does not use the 64-bit extension as a target and does not assert
ACK64#. PI7C8154A does not assert ACK64# under any of the following conditions:
!
!
!
!
!
If PI7C8154A is the target of a 64-bit memory write transaction, it is able to accept 64 bits of data
during each data phase. If PI7C8154A is the target of a memory read transaction, it delivers 64 bits
of read data during each data phase and drives PAR64 corresponding to AD[63:32] and CBE[7:4]
for each data phase. If an odd number of DWORDS is read from the target and PI7C8154A has
asserted ACK64# when returning read data to the initiator, PI7C8154A disconnects before the last
DWORD is returned. PI7C8154A may have read an odd number of DWORD’s because of either a
target disconnect or a master latency timer expiration during 32-bit data transfers on the opposite
interface.
64-BIT TRANSACTIONS – SUPPORT DURING RESET
PI7C8154A checks P_REQ64# while P_RESET# is asserted to determine whether the 64-bit
extensions are connected. If P_REQ64# is HIGH, PI7C8154A knows that the 64-bit extension
signals are not connected so it always drives the 64-bit extension outputs to have valid logic levels
on the inputs. PI7C8154A will then treat all transactions on the primary as 32-bit. If P_REQ64# is
LOW, the 64-bit signals should be connected to pull-up resistors on the board and PI7C8154A does
not perform any input biasing. PI7C8154A can then treat memory write and prefetchable memory
read transactions as 64-bit transactions on the primary.
REQ64# was not asserted by the initiator
PI7C8154A is responding to a non-prefetchable memory read transaction
PI7C8154A is responding to an I/O transaction
PI7C8154A is responding to a configuration transaction
Only 1 DWORD of data was read from the target
Page 36 of 112
ASYNCHRONOUS 2-PORT
JULY 2004 REVISION 1.00
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A