pi7c8154a Pericom Semiconductor Corporation, pi7c8154a Datasheet - Page 10
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pi7c8154a
Manufacturer Part Number
pi7c8154a
Description
2-port Pci-to-pci Bridge
Manufacturer
Pericom Semiconductor Corporation
Datasheet
1.PI7C8154A.pdf
(112 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
pi7c8154aNAE
Manufacturer:
XILINX
Quantity:
192
LIST OF TABLES
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LIST OF FIGURES
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04
......................................................................................................................................................................59
2-1 PCI TRANSACTIONS........................................................................................................................23
2-2 WRITE TRANSACTION FORWARDING........................................................................................24
2-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES .............................................27
2-4 READ PREFETCH ADDRESS BOUNDARIES ................................................................................29
2-5 READ TRANSACTION PREFETCHING .........................................................................................29
2-6 DEVICE NUMBER TO IDSEL S_AD PIN MAPPING......................................................................33
2-7 DELAYED WRITE TARGET TERMINATION RESPONSE ...........................................................41
2-8 RESPONSE TO POSTED WRITE TARGET TERMINATION.........................................................41
2-9 RESPONSE TO DELAYED READ TARGET TERMINATION.......................................................42
4-1 SUMMARY OF TRANSACTION ORDERING .................................................................................51
5-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT (
5-2 SETTING THE SECONDARY INTERFACE DETECTED PARITY ERROR BIT ..........................58
5-3 SETTING THE PRIMARY INTERFACE DATA PARITY DETECTED BIT (
5-4 SETTING THE SECONDARY INTERFACE DATA PARITY DETECTED BIT.............................59
5-5 ASSERTION OF P_PERR# ................................................................................................................60
5-6 ASSERTION OF S_PERR# ................................................................................................................60
5-7 ASSERTION OF P_SERR# FOR DATA PARITY ERRORS ............................................................61
8-1 GPIO OPERATION ............................................................................................................................69
8-2 GPIO SERIAL DATA FORMAT........................................................................................................69
12-1 POWER MANAGEMENT TRANSITIONS.....................................................................................73
14-1 CONFIGURATION SPACE MAP....................................................................................................76
16-1 TAP PINS........................................................................................................................................103
16-2 JTAG BOUNDARY REGISTER ORDER......................................................................................105
7-1 SECONDARY ARBITER EXAMPLE ..............................................................................................66
16-1 TEST ACCESS PORT DIAGRAM................................................................................................102
17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS...........................................................109
18-1 304-BALL PBGA PACKAGE OUTLINE .....................................................................................112
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Page 10 of 112
ASYNCHRONOUS 2-PORT
JULY 2004 REVISION 1.00
BIT
PCI-to-PCI BRIDGE
BIT
Advance Information
24
31
OF OFFSET
OF OFFSET
PI7C8154A
04
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