pi7c8154a Pericom Semiconductor Corporation, pi7c8154a Datasheet - Page 37

• Manufacturer Part Number: pi7c8154a
• Description: 2-port Pci-to-pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

2.10
2.11
PI7C8154A always asserts S_REQ64# LOW during S_RESET# to indicate that the 64-bit
extension is supported on the secondary bus. Individual pull-up resistors must always be supplied
for S_AD[63:32], S_CBE[7:4], and S_PAR64.
TRANSACTION FLOW THROUGH
Transaction flow through refers to data being removed from the read/write buffers concurrently as
data is still being written to the buffer.
For reads, flow through occurs when the initiator repeats the delayed transaction while some read
data is in the buffer, but the transaction is still ongoing on the target bus. For read flow through to
occur, there can be no other reads or writes previously posted in the same direction.
For writes, flow through occurs when PI7C8154A is able to arbitrate for the target bus, initiate the
transaction and receive TRDY# from the target, while receiving data from the same transaction on
the initiator bus. Flow through can only occur if the writes that were previously posted in the same
direction are completed.
TRANSACTION TERMINATION
This section describes how PI7C8154A returns transaction termination conditions back to the
initiator.
The initiator can terminate transactions with one of the following types of termination:
!
Normal termination occurs when the initiator de-asserts FRAME# at the beginning of the last data
phase, and de-asserts IRDYL at the end of the last data phase in conjunction with either TRDY# or
STOP# assertion from the target.
!
A master abort occurs when no target response is detected. When the initiator does not detect a
DEVSEL# from the target within five clock cycles after asserting FRAME#, the initiator terminates
the transaction with a master abort. If FRAME# is still asserted, the initiator de-asserts FRAME#
on the next cycle, and then de-asserts IRDY# on the following cycle. IRDY# must be asserted in
the same cycle in which FRAME# deasserts. If FRAME# is already deasserted, IRDY# can be
deasserted on the next clock cycle following detection of the master abort condition.
The target can terminate transactions with one of the following types of termination:
!
TRDY# and DEVSEL# asserted in conjunction with FRAME# deasserted and IRDY# asserted.
!
STOP# and DEVSEL# asserted with TRDY# deasserted during the first data phase. No data
transfers occur during the transaction. This transaction must be repeated.
!
STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer of the
transaction.
Normal termination
Master abort
Normal termination
Target retry
Target disconnect with data transfer
Page 37 of 112
ASYNCHRONOUS 2-PORT
JULY 2004 REVISION 1.00
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A