pi7c8154a Pericom Semiconductor Corporation, pi7c8154a Datasheet - Page 24

• Manufacturer Part Number: pi7c8154a
• Description: 2-port Pci-to-pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

2.3
2.4
2.5
2.6
DUAL ADDRESS PHASE
A 64-bit address uses two address phases. The first address phase is denoted by the asserting edge
of FRAME#. The second address phase always follows on the next clock cycle.
For a 32-bit interface, the first address phase contains dual address command code on the CBE[3:0]
lines, and the low 32 address bits on the AD[31:0] lines. The second address phase consists of the
specific memory transaction command code on the CBE[3:0] lines, and the high 32 address bits on
the AD[31:0] lines. In this way, 64-bit addressing can be supported on 32-bit PCI buses.
The PCI-to-PCI Bridge Architecture Specification supports the use of dual address transactions in
the prefetchable memory range only. See Section 3.3.3 for a discussion of prefetchable address
space. The PI7C8154A supports dual address transactions in both the upstream and the downstream
direction. The PI7C8154A supports a programmable 64-bit address range in prefetchable memory
for downstream forwarding of dual address transactions. Dual address transactions falling outside
the prefetchable address range are forwarded upstream, but not downstream. Prefetching and
posting are performed in a manner consistent with the guidelines given in this document for each
type of memory transaction in prefetchable memory space.
DEVICE SELECT (DEVSEL#) GENERATION
PI7C8154A always performs positive address decoding (medium decode) when accepting
transactions on either the primary or secondary buses. PI7C8154A never does subtractive decode.
DATA PHASE
The address phase of a PCI transaction is followed by one or more data phases. A data phase is
completed when IRDY# and either TRDY# or STOP# are asserted. A transfer of data occurs only
when both IRDY# and TRDY# are asserted during the same PCI clock cycle. The last data phase of
a transaction is indicated when FRAME# is de-asserted and both TRDY# and IRDY# are asserted,
or when IRDY# and STOP# are asserted. See Section 2.11 for further discussion of transaction
termination.
Depending on the command type, PI7C8154A can support multiple data phase PCI transactions.
For detailed descriptions of how PI7C8154A imposes disconnect boundaries, see Section 2.6.4 for
write address boundaries and Section 2.7.3 read address boundaries.
WRITE TRANSACTIONS
Write transactions are treated as either posted write or delayed write transactions. Table 2-2 shows
the method of forwarding used for each type of write operation.
Table 2-2 WRITE TRANSACTION FORWARDING
Type of Transaction
Memory Write
Memory Write and Invalidate
Memory Write to VGA memory
I/O Write
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Type of Forwarding
Posted (except VGA memory)
Posted
Delayed
Delayed
ASYNCHRONOUS 2-PORT
JULY 2004 REVISION 1.00
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A