pi7c8154a Pericom Semiconductor Corporation, pi7c8154a Datasheet - Page 60

• Manufacturer Part Number: pi7c8154a
• Description: 2-port Pci-to-pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

Note: x=don’t care
Table 5-5 shows assertion of P_PERR#. This signal is set under the following conditions:
!
!
!
Table 5-5 ASSERTION OF P_PERR#
Notes: x=don’t care
Table 5-6 shows assertion of S_PERR# that is set under the following conditions:
!
!
!
Table 5-6 ASSERTION OF S_PERR#
0
0
0
1
0
0
1 (de-asserted)
1
0 (asserted)
1
0
1
1
1
0
0
1
1
1 (de-asserted)
0 (asserted)
1
1
1
1
1
0
1
2
Detected Parity
Detected Bit
Secondary
PI7C8154A is either the target of a write transaction or the initiator of a read transaction on the
primary bus.
The parity-error-response bit must be set in the command register of primary interface.
PI7C8154A detects a data parity error on the primary bus or detects S_PERR# asserted during
the completion phase of a downstream delayed write transaction on the target (secondary) bus.
PI7C8154A is either the target of a write transaction or the initiator of a read transaction on the
secondary bus.
The parity error response bit must be set in the bridge control register of secondary interface.
PI7C8154A detects a data parity error on the secondary bus or detects P_PERR# asserted
during the completion phase of an upstream delayed write transaction on the target (primary)
bus.
P_PERR#
S_PERR#
2
=The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Transaction Type
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
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Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Direction
Direction
Direction
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Bus Where Error
Bus Where Error
Bus Where Error
Was Detected
Was Detected
Was Detected
ASYNCHRONOUS 2-PORT
JULY 2004 REVISION 1.00
x / x
x / 1
x / x
x / x
x / x
x / x
x / x
x / 1
x / x
Primary / Secondary Parity
Primary/ Secondary Parity
Primary/ Secondary Parity
Error Response Bits
Error Response Bits
Error Response Bits
PCI-to-PCI BRIDGE
Advance Information
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / x
1 / x
x / x
1 / x
x / x
x / x
x / x
1 / x
1 / 1
x / x
x / x
PI7C8154A