pi7c8154a Pericom Semiconductor Corporation, pi7c8154a Datasheet - Page 23

• Manufacturer Part Number: pi7c8154a
• Description: 2-port Pci-to-pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

2.1
2.2
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by PI7C8154A. Table 2-1 lists the
command code and name of each PCI transaction. The Master and Target columns indicate support
for each transaction when PI7C8154A initiates transactions as a master, on the primary and
secondary buses, and when PI7C8154A responds to transactions as a target, on the primary and
secondary buses.
Table 2-1 PCI TRANSACTIONS
As indicated in Table 2-1, the following PCI commands are not supported by PI7C8154A:
!
!
!
!
SINGLE ADDRESS PHASE
A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and the bus
command is driven on P_CBE[3:0]. PI7C8154A supports the linear increment address mode only,
which is indicated when the lowest two address bits are equal to zero. If either of the lowest two
address bits is nonzero, PI7C8154A automatically disconnects the transaction after the first data
transfer.
Types of Transactions
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PI7C8154A never initiates a PCI transaction with a reserved command code and, as a target,
PI7C8154A ignores reserved command codes.
PI7C8154A does not generate interrupt acknowledge transactions. PI7C8154A ignores
interrupt acknowledge transactions as a target.
PI7C8154A does not respond to special cycle transactions. PI7C8154A cannot guarantee
delivery of a special cycle transaction to downstream buses because of the broadcast nature of
the special cycle command and the inability to control the transaction as a target. To generate
special cycle transactions on other PCI buses, either upstream or downstream, Type 1
configuration write must be used.
PI7C8154A neither generates Type 0 configuration transactions on the primary PCI bus nor
responds to Type 0 configuration transactions on the secondary PCI bus.
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
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Initiates as Master
Primary
N
Y
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
Secondary
N
Y
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
ASYNCHRONOUS 2-PORT
JULY 2004 REVISION 1.00
Responds as Target
N
N
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Primary
Y
PCI-to-PCI BRIDGE
Advance Information
Secondary
N
N
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
PI7C8154A