pi7c8154a Pericom Semiconductor Corporation, pi7c8154a Datasheet - Page 27

• Manufacturer Part Number: pi7c8154a
• Description: 2-port Pci-to-pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

2.6.4
2.6.5
2.6.6
2.7
If the initiator does not repeat the delayed write transaction before the discard timer expires,
PI7C8154A discards the delayed write completion from the delayed transaction completion queue.
PI7C8154A also conditionally asserts P_SERR# (see Section 5.4).
WRITE TRANSACTION ADDRESS BOUNDARIES
PI7C8154A imposes internal address boundaries when accepting write data. The aligned address
boundaries are used to prevent PI7C8154A from continuing a transaction over a device address
boundary and to provide an upper limit on maximum latency. PI7C78154 returns a target
disconnect to the initiator when it reaches the aligned address boundaries under conditions shown
in Table 2-3.
Table 2-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES
Note 1. Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the configuration space.
BUFFERING MULTIPLE WRITE TRANSACTIONS
PI7C8154A continues to accept posted memory write transactions as long as space for at least one
DWORD of data in the posted write data buffer remains. If the posted write data buffer fills before
the initiator terminates the write transaction, PI7C8154A returns a target disconnect to the initiator.
Delayed write transactions are accepted as long as at least one open entry in the delayed transaction
queue exists. Therefore, several posted and delayed write transactions can exist in data buffers at
the same time. See Chapter 4 for information about how multiple posted and delayed write
transactions are ordered.
FAST BACK-TO-BACK TRANSACTIONS
PI7C8154A is capable of decoding and forwarding fast back-to-back write transactions. When
PI7C8154A cannot accept the second transaction because of buffer space limitations, it returns a
target retry to the initiator. The fast back-to-back enable bit must be set in the command register for
upstream write transactions, and in the bridge control register for downstream write transactions.
READ TRANSACTIONS
Type of Transaction
Delayed Write
Posted Memory Write
Posted Memory Write
Posted Memory Write and
Invalidate
Posted Memory Write and
Invalidate
Posted Memory Write and
Invalidate
Condition
All
Memory write disconnect control
bit = 0
Memory write disconnect control
bit = 1
Cache line size ≠ 1, 2, 4, 8, 16
Cache line size = 1, 2, 4, 8
Cache line size = 16
(1)
(1)
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Aligned Address Boundary
Disconnects after one data transfer
4KB aligned address boundary
Disconnects at cache line boundary
4KB aligned address boundary
Cache line boundary if posted memory write data
FIFO does not have enough space for the next
cache line
16-DWORD aligned address boundary
ASYNCHRONOUS 2-PORT
JULY 2004 REVISION 1.00
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A