mt46h8m16lfcf-75-it Micron Semiconductor Products, mt46h8m16lfcf-75-it Datasheet - Page 67
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mt46h8m16lfcf-75-it
Manufacturer Part Number
mt46h8m16lfcf-75-it
Description
128mb Mobile Ddr Sdram Mt46h4m32lfb5-6
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT46H8M16LFCF-75-IT.pdf
(84 pages)
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Figure 38:
PDF: 09005aef8331b3e9 / Source: 09005aef8331b3ce
ddr_mobile_sdram_cmd_op_timing_dia_fr5.08__3.fm - Rev. B 06/08 EN
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE-to-READ – Interrupting
Notes:
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
1. D
2. An interrupted burst of 4 is shown; two data elements are written.
3.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T2 and T2n (nominal case) to register DM.
t
D
WTR is referenced from the first positive CK edge after the last data-in pair.
b
IN
IN
NOP
b = data-in for column b; D
D
T1
b
IN
b+1
D
D
b
IN
IN
T1n
b+1
D
IN
b+1
D
IN
NOP
T2
t
WTR
T2n
67
Bank a,
OUT
READ
Col n
T3
n = data-out for column n.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16, x32 Mobile DDR SDRAM
T4
NOP
Don’t Care
CL = 3
CL = 3
CL = 3
T5
NOP
©2007 Micron Technology, Inc. All rights reserved.
T5n
Transitioning Data
Timing Diagrams
D
D
D
OUT
n
OUT
n
OUT
n
T6
NOP
D
n + 1
D
Preliminary
n + 1
D
n + 1
OUT
OUT
OUT
T6n
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